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blackfin and the blackfi n logo are registered tradem arks of analog devices, inc. blackfin embedded processor adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o.box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 analog devices, inc. all rights reserved. features up to 600 mhz high performance blackfin processor two 16-bit macs, two 40-bit alus, four 8-bit video alus risc-like register and instruction model wide range of operating volt ages and flexible booting options programmable on-chip voltage regulator 400-ball csp_bga, rohs compliant package memory up to 324k bytes of on-c hip memory comprised of instruction sram/cache; dedicated instruction sram; data sram/cache; dedicated data sram; scratchpad sram external sync memory contro ller supporting either ddr sdram or mobile ddr sdram external async memory controller supporting 8-/16-bit async memories and burst flash devices nand flash controller 4 memory-to-memory dma pairs, 2 with ext. requests memory management unit providing memory protection code security with lockbox secure technology and 128-bit aes/arc4 data encryption one-time-programmable (otp) memory peripherals high speed usb on-the-go (otg) with integrated phy sd/sdio controller ata/atapi-6 controller up to 4 synchronous serial ports (sports) up to 3 serial peripheral interfaces (spi-compatible) up to 4 uarts, two with automatic h/w flow control up to 2 can (controller area network) 2.0b interfaces up to 2 twi (2-wire interface) controllers 8- or 16-bit asynchrono us host dma interface multiple enhanced parallel peripheral interfaces (eppis), supporting itu-r bt.656 video formats and 18-/24-bit lcd connections media transceiver (mxvr) for connection to a most network pixel compositor for overlays, alpha blending, and color conversion up to eleven 32-bit timers/counters with pwm support real-time clock (rtc) and watchdog timer up/down counter with supp ort for rotary encoder up to 152 general-purpose i/o (gpios) on-chip pll capable of frequency multiplication debug/jtag interface figure 1. adsp-bf549 fu nctional block diagram can (0-1) twi (0-1) timers(0-10) keypad counter rtc host dma jtag test and emulation uart (2-3) external port nor, ddr, mddr spi (2) sport (0-1) sd / sdio watchdog timer boot rom 32 16 pixel compositor voltage regulator eppi (0-2) sport (2-3) spi (0-1) uart (0-1) ports pa b usb 16-bit dma 32-bit dma interrupts l2 sram l1 instr rom l1 instr sram l1 data sram dab1 dab0 ports otp 16 16 ddr/mddr async 16 nand flash controller atapi mxvr dcb 32 eab 64 deb 32 b
rev. d | page 2 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 table of contents general description ................................................. 3 low power architecture ......................................... 4 system integration ................................................ 4 blackfin processor peripherals ................................. 4 blackfin processor core .......................................... 4 memory architecture ............................................ 6 dma controllers .................................................. 9 real-time clock ................................................. 10 watchdog timer ................................................ 10 timers ............................................................. 10 up/down counter and thumbwheel interface .......... 11 serial ports (sports) .......................................... 11 serial peripheral interface (spi) ports ...................... 11 uart ports (uarts) .......................................... 11 controller area network (can) ............................ 12 twi controller interface ...................................... 12 ports ................................................................ 12 pixel compositor (pixc) ...................................... 13 enhanced parallel peripheral interface (eppi) ........... 13 usb on-the-go dual-role device controller ............ 13 ata/atapi-6 interface ....................................... 14 keypad interface ................................................. 14 secure digital (sd)/sdio controller ....................... 14 code security ..................................................... 14 media transceiver mac layer (mxvr) ................... 14 dynamic power management ................................ 15 voltage regulation .............................................. 16 clock signals ...................................................... 17 booting modes ................................................... 18 instruction set description .................................... 21 development tools .............................................. 21 designing an emulator-compa tible processor board ... 21 mxvr board layout guidelines ............................. 21 related documents .............................................. 22 related signal chains ........................................... 22 lockbox secure technology disclaimer .................... 22 pin descriptions .................................................... 23 specifications ........................................................ 33 400-ball csp_bga package ... ................................... 92 outline dimensions ................................................ 98 surface-mount design .......................................... 98 automotive products .............................................. 99 ordering guide ..................................................... 99 revision history 5/11rev. c to rev. d numerous small corrections and additions to document. major changes/additions include: added several extended temper ature models. for more infor- mation, see ordering guide ...................................... 99 added new text for pin descriptions in pin descriptions .. 23 added 400 mhz junction temperat ure to parameter column of the operating conditions table in specifications ............ 33 updated table 15 to include informatio n on extended tempera- ture grade parts. see system clock requirements ........... 34 data in the nonautomotive 400 mhz column of electrical characteristics also applies to extended temperature grade as noted in footnote 1. see electrical characteristics .......... 35 updated table 23 to reflect rohs compliant part is optional. see package information ......................................... 40 updated table 31 to reflect extended temperature grade part. see ddr sdram/mobile ddr sdram clock and control cycle timing ........................................................ 47 added timer clock timing specification table ( table 47 ) and fig- ure ( figure 41 ). see timer clock timing ...................... 66 updated package diagram to correct jedec specification and outdated coplanarity number. see outline dimensions .... 98 to view product/process change notifications (pcns) related to this data sheet revision, please visit the processor's product page on the www.analog.com website and use the view pcn link.
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 3 of 100 | may 2011 general description the adsp-bf54x blackfin ? processors are members of the blackfin family of products, incorporating the analog devices/ intel micro signal architecture (msa). blackfin processors combine a dual-mac state-of-the-a rt signal processing engine, the advantages of a clean, orth ogonal risc-like microprocessor instruction set, and single-ins truction, multiple-data (simd) multimedia capabili ties into a single instruction-set architecture. specific performance, memory configurations, and features of adsp-bf54x blackfin processors are shown in table 1 . specific peripherals for adsp-b f54x blackfin processors are shown in table 2 . table 1. adsp-bf54x processor features processor features adsp-bf549 adsp-bf548 adsp-bf547 adsp-bf544 adsp-bf542 lockbox ? 1 code security 1 lockbox is a registered trademark of analog devices, inc. 11111 128-bit aes/ arc4 data encryption 11111 sd/sdio controller 1 1 1 C 1 pixel compositor 1 1 1 1 1 18- or 24-bit eppi0 with lcd 1 1 1 1 C 16-bit eppi1, 8-bit eppi2 1 1 1 1 1 host dma port 1 1 1 1 C nand flash controller 1 1 1 1 1 atapi 111C1 high speed usb otg 1 1 1 C 1 keypad interface 1 1 1 C 1 mxvr 1 C C C C can ports 2 2 C 2 1 twi ports 22221 spi ports 33322 uart ports 44433 sports 44433 up/down counter 11111 timers 11 11 11 11 8 general-purpose i/o pins 152 152 152 152 152 memory configura- tions (k bytes) l1 instruction sram/cache 16 16 16 16 16 l1 instruction sram 48 48 48 48 48 l1 data sram/cache 32 32 32 32 32 l1 data sram 32 32 32 32 32 l1 scratchpad sram 44444 l1 rom 2 2 this rom is not customer-configurable. 64 64 64 64 64 l2 128 128 128 64 C l3 boot rom 2 44444 maximum core instruction rate (mhz) 533 533 600 533 600 table 2. specific peripherals for adsp-bf54x processors module adsp-bf549 adsp-bf548 adsp-bf547 adsp-bf544 adsp-bf542 ebiu (async) ppppp nand flash controller ppppp atapi pppCp host dma port (hostdp) ppppC sd/sdio controller p p p C p eppi0 ppppC eppi1 ppppp eppi2 ppppp sport0 pppCC sport1 ppppp sport2 ppppp sport3 ppppp spi0 ppppp spi1 ppppp spi2 pppCC uart0 ppppp uart1 ppppp uart2 pppCC uart3 ppppp high speed usb otg pppCp can0 p p C p p can1 p p C p C twi0 ppppp twi1 ppppC timer 0C7 ppppp timer 8C10 ppppC up/down counter ppppp keypad interface p p p C p mxvr pCCCC gpios ppppp
rev. d | page 4 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 the adsp-bf54x blackfin proce ssors are completely code- and pin-compatible. they differ only with respect to their perfor- mance, on-chip memory, and se lection of i/o peripherals. specific performance, memory, and feature configurations are shown in table 1 . by integrating a rich set of indu stry-leading syst em peripherals and memory, blackfin processors are the platform of choice for next-generation applications that require risc-like program- mability, multimedia support , and leading- edge signal processing in one integrated package. low power architecture blackfin processors provide world-class power management and performance. blackfin processors are designed in a low power and low voltage design methodology and feature on-chip dynamic power management, the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. reducing both voltage and frequency can result in a substantial reduction in power consumption as compared to reducing only the frequency of operation. this translates into longer battery life fo r portable appliances. system integration the adsp-bf54x blackfin processors are highly integrated system-on-a-chip solutions for the next generation of embed- ded network connected applications. by combining industry- standard interfaces with a high performance signal processing core, users can develop cost-effe ctive solutions quickly without the need for costly external co mponents. the system peripherals include a high speed usb otg (on-the-go) co ntroller with integrated phy, can 2.0b cont rollers, twi controllers, uart ports, spi ports, serial port s (sports), atapi controller, sd/sdio controller, a real-time clock, a watchdog timer, lcd controller, and multiple enhanced parallel peripheral interfaces. blackfin processor peripherals the adsp-bf54x processors cont ain a rich set of peripherals connected to the core via several high bandwidth buses, provid- ing flexibility in system configur ation as well as excellent overall system performance (see figure 1 on page 1 ). the general- purpose peripherals include functions such as uarts, spi, twi, timers with pulse width modulation (pwm) and pulse measurement capability, general- purpose i/o pins, a real-time clock, and a watchdog timer. th is set of functions satisfies a wide variety of typical system support needs and is augmented by the system expansion capabilities of the part. the adsp- bf54x processors contain dedi cated network communication modules and high speed serial a nd parallel ports, an interrupt controller for flexible management of interrupts from the on- chip peripherals or external sources, and power management control functions to tailor th e performance and power charac- teristics of the processor and system to many application scenarios. all of the peripherals, except for general-purpose i/o, can, twi, real-time clock, and timers , are supported by a flexible dma structure. there are also separate memory dma channels dedicated to data transfers be tween the processor's various memory spaces, including external ddr (either standard or mobile, depending on the device) and asynchronous memory. multiple on-chip buses running at up to 133 mhz provide enough bandwidth to keep the processor core running along with activity on all of the on -chip and external peripherals. the adsp-bf54x blackfin processors include an on-chip volt- age regulator in support of the dynamic power management capability. the voltage regulator provides a range of core volt- age levels when supplied from v ddext . the voltage regulator can be bypassed at the users discretion. blackfin processor core as shown in figure 2 on page 5 , the blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit alus, four video alus, an d a 40-bit shifter. the compu- tation units process 8-, 16-, or 32-b it data from the register file. the compute register file contai ns eight 32-bit registers. when performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. all operands for compute operations come from the multiported register file and instruction constant fields. each mac can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. signed and unsigned formats, rounding, and saturation are supported. the alus perform a traditional set of arithmetic and logical operations on 16- or 32-bit data. in addition, many special instructions are included to acce lerate various signal processing tasks. these include bit operations such as field extract and pop- ulation count, modulo 2 32 multiply, divide primitives, saturation and rounding, and sign/exponent detection. the set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with cli pping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (saa) operations. also provided are the compar e/select and vector search instructions. for certain instructions, two 16-bit alu operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute regi ster). by also using the second alu, quad 16-bit operations are possible. the 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. the program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. for program flow control, the sequ encer supports pc relative and indirect conditional jumps (with static branch prediction), and subroutine calls. hardware is provided to support zero-over- head looping. the architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. the address arithmetic unit provides two addresses for simulta- neous dual fetches from memory. it contains a multiported register file consisting of four sets of 32-bit index, modify,
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 5 of 100 | may 2011 length, and base registers (for circular buffering), and eight additional 32-bit pointer regist ers (for c-style indexed stack manipulation). blackfin processors support a modified harvard architecture in combination with a hierarchical memory structure. level 1 (l1) memories are those that typically operate at the full processor speed with little or no latency. at the l1 level, the instruction memory holds instructions only. the two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. in addition, multiple l1 memory blocks are provided, offering a configurable mix of sram and cache. the memory manage- ment unit (mmu) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. the architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. user mode has restricted access to certain syst em resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. the blackfin processor instruct ion set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent compiled code density. complex dsp instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. blackfin processors support a limited multi-issue ca pability, where a 32-bit instruc- tion can be issued in paralle l with two 16-bit instructions, allowing the programmer to use ma ny of the core resources in a single instruction cycle. the blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. the architecture has been optimized for use in conjunction with the c/c++ compiler, resulting in fast and effici ent software implementations. figure 2. blackfin processor core sequencer align decode loop buffer 16 16 8 888 40 40 a0 a1 barrel shifter data arithmetic unit control unit r7.h r6.h r5.h r4.h r3.h r2.h r1.h r0.h r7.l r6.l r5.l r4.l r3.l r2.l r1.l r0.l astat 40 40 32 32 32 32 32 32 32 ld0 ld1 sd dag0 dag1 address arithmetic unit i3 i2 i1 i0 l3 l2 l1 l0 b3 b2 b1 b0 m3 m2 m1 m0 sp fp p5 p4 p3 p2 p1 p0 da1 da0 32 32 32 preg rab 32 to memory
rev. d | page 6 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 memory architecture the adsp-bf54x processors view memory as a single unified 4g byte address space, using 32- bit addresses. all resources, including internal memory, external memory, and i/o control registers, occupy separate sect ions of this common address space. the memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low- latency on-chip memory as cache or sram, and larger, lower-cost and performance off-chip memory systems. see figure 3 on page 6 . the on-chip l1 memory system is the highest-performance memory available to the blackfin processor. the off-chip mem- ory system, accessed through the external bus interface unit (ebiu), provides expansion with flash memory, sram, and double-rate sdram (standard or mobile ddr), optionally accessing up to 768m bytes of physical memory. most of the adsp-bf54x blackfin processors also include an l2 sram memory array wh ich provides up to 128k bytes of high speed sram, operating at one half the frequency of the core and with slightly longer latency th an the l1 memory banks (for information on l2 memory in each processor, see table 1 ). the l2 memory is a unified instruction and data memory and can hold any mixture of code and data required by the system design. the blackfin cores share a dedicated low latency 64-bit data path port into the l2 sram memory. the memory dma controllers (dmac1 and dmac0) provide high-bandwidth data-movement capability. they can perform block transfers of code or data between the internal memory and the external memory spaces. internal (on-chip) memory the adsp-bf54x processors have several blocks of on-chip memory providing high bandwidth access to the core. the first block is the l1 instruction memory, consisting of 64k bytes of sram, of which 16k bytes can be configured as a four-way set-associat ive cache or as sram. this memory is accessed at full processor speed. the second on-chip memory block is the l1 data memory, con- sisting of 64k bytes of sram, of which 32k bytes can be configured as a two-way set-asso ciative cache or as sram. this memory block is accessed at full processor speed. the third memory block is a 4k byte scratchpad sram, which runs at the same speed as the l1 memories. it is only accessible as data sram and cannot be configured as cache memory. the fourth memory block is the factory programmed l1 instruction rom, operating at full processor speed. this rom is not customer-configurable. the fifth memory block is the l2 sram, providing up to 128k bytes of unified instruction and data memory, operating at one half the frequency of the core. finally, there is a 4k byte boot rom connected as l3 memory. it operates at full sclk rate. external (off-chip) memory through the external bus interface unit (ebiu), the adsp-bf54x blackfin processors provide glueless connectivity to external 16-bit wide memories, such as ddr and mobile ddr sdram, sram, nor flash, nand flash, and fifo devices. to provide the best perf ormance, the bus system of the ddr and mobile ddr interface is completely separate from the other parallel interfaces. furthe rmore, the ddr controller sup- ports either standard ddr memory or mobile ddr memory. see the ordering guide on page 99 for details. throughout this document, references to ddr are intended to cover both the standard and mobile ddr standards. figure 3. adsp-bf547/adsp-bf548/adsp-bf549 internal/external memory map 1 1 for adsp-bf544 processors, l2 sram is 64k bytes (0xfeb0000?0xfeb0ffff). for adsp-bf542 processors, there is no l2 sram. reserved core mmr registers (2m bytes) reserved scratchpad sram (4k bytes) instruction bank b sra m (16k bytes) system mmr registers (2m bytes) reserved reserved data bank b sram / cache (16k bytes) data bank b sram (16 k bytes) data bank a sram / cache (16k bytes) async memory bank 3 (64m bytes) async memory bank 2 (64m bytes) async memory bank 1 (64m bytes) async memory bank 0 (64m bytes) ddr mem bank 0 (8m bytes to 256m bytes) instruction sram / cache (16k bytes) internal memory map external memory map ffff ffff feb0 0000 ffb0 0000 ffa2 4000 ffa1 0000 ff90 8000 ff90 4000 ff80 8000 ff80 4000 3000 0000 2c00 0000 2800 0000 2400 0000 2000 0000 ef00 0000 0000 0000 ffc0 0000 ffb0 1000 ffa0 0000 data bank a sram (16 k bytes) ff90 0000 ff80 0000 reserved reserved c000 ffa0 8000 instruction bank a sra m (32k bytes) reserved b oot rom (4k bytes) ef00 1000 ffe0 0000 feb2 0000 ffa1 4000 l1 rom (64k byte) l2 sram (128k bytes) ddr mem bank 1 (8m bytes to 256m bytes) reserved top of last ddr page reserved ffa0 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0 x 0x 0x 0x 0x 0x 0x 0x 0x
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 7 of 100 | may 2011 the ddr memory controller can gluelessly manage up to two banks of double-rate synchronous dynamic memory (ddr and mobile ddr sdram). the 16-bit interface operates at the sclk frequency, enabling a maximum throughput of 532m bytes/s. the ddr and mobile ddr controller is augmented with a queuing mechanism that performs efficient bursts into the ddr and mobile ddr. the cont roller is an industry stan- dard ddr and mobile ddr sdra m controller with each bank supporting from 64m bit to 512m bi t device sizes and 4-, 8-, or 16-bit widths. the controller su pports up to 256m bytes per external bank. with 2 external banks, the controller supports up to 512m bytes total. each bank is independently programmable and is contiguous with adjacent banks regardless of the sizes of the different banks or their placement. traditional 16-bit as ynchronous memories, such as sram, eprom, and flash devices, can be connected to one of the four 64m byte asynchronous memory banks, represented by four memory select strobes. alternativ ely, these strobes can function as bank-specific read or write strobes preventing further glue logic when connecting to asynch ronous fifo devices. see the ordering guide on page 99 for a list of specific products that provide support for ddr memory. in addition, the external bus can connect to advanced flash device technologies, such as: ? page-mode nor flash devices ? synchronous burst-mode nor flash devices ?nand flash devices customers should consult the ordering guide when selecting a specific adsp-bf54x component for the intended application. products that provide support for mobile ddr memory are noted in the ordering guide footnotes. nand flash controller (nfc) the adsp-bf54x blackfin processors provide a nand flash controller (nfc) as part of the external bus interface. nand flash devices provide high-densi ty, low-cost memory. however, nand flash devices also have long random access times, invalid blocks, and lower reliability over device lifetimes. because of this, nand flash is often used for read-only code storage. in this case, all dsp code can be stored in nand flash and then transferred to a faster memory (such as ddr or sram) before execution. another common use of nand flash is for storage of multimedia files or other larg e data segments. in this case, a software file system may be used to manage reading and writing of the nand flash device. the fi le system selects memory seg- ments for storage with the goal of avoiding bad blocks and equally distributing memory ac cesses across all address loca- tions. hardware features of the nfc include: ? support for page program, pa ge read, and block erase of nand flash devices, with accesses aligned to page boundaries. ? error checking and correction (ecc) hardware that facili- tates error detection and correction. ? a single 8-bit or 16-bit external bus interface for com- mands, addresses, and data. ? support for slc (single level cell) nand flash devices unlimited in size, with page sizes of 256 bytes and 512 bytes. larger page sizes can be supported in software. ? the ability to release external bus interface pins during long accesses. ? support for internal bus requests of 16 bits or 32 bits. ? a dma engine to transfer da ta between internal memory and a nand flash device. one-time-programmable memory the adsp-bf54x blackfin proce ssors have 64k bits of one- time-programmable (otp) non-volatile memory that can be programmed by the developer only one time. it includes the array and logic to support read access and programming. addi- tionally, its pages can be write protected. otp enables developers to store both public and private data on-chip. in addition to storing public and private key data for applications requiring security, it also allows developers to store completely user-definable data such as a customer id, product id, or a mac address. by using th is feature, generic parts can be shipped, which are then prog rammed and protected by the developer within this non-volatile memory. the otp memory can be accessed through an api provided by the on-chip rom. i/o memory space the adsp-bf54x blackfin processo rs do not define a separate i/o space. all resources are mapped through the flat 32-bit address space. on-chip i/o device s have their control registers mapped into memory-mapped regi sters (mmrs) at addresses near the top of the 4g byte addr ess space. these are separated into two smaller blocks, one containing the control mmrs for all core functions and the other containing the registers needed for setup and control of the on-chip peripherals outside of the core. the mmrs are accessible on ly in supervisor mode and appear as reserved spac e to on-chip peripherals. booting the adsp-bf54x blackfin processors contain a small on-chip boot kernel, which configures the appropriate peripheral for booting. if the adsp-bf54x blac kfin processors are configured to boot from boot rom memory space, the processor starts exe- cuting from the on-chip boot rom. for more information, see booting modes on page 18 . event handling the event controller on the adsp -bf54x blackfin processors handles all asynchronous and sync hronous events to the proces- sors. the adsp-bf54x blackfin processors provide event handling that supports both nest ing and prioritization. nesting allows multiple event service ro utines to be active simultane- ously. prioritization ensures that servicing of a higher-priority event takes precedence over servic ing of a lower-priority event.
rev. d | page 8 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 the controller provides support for five different types of events: ? emulation. an emulation even t causes the processor to enter emulation mode, allowing command and control of the processor via the jtag interface. ? reset. this event resets the processor. ? non-maskable interrupt (nmi). the nmi event can be generated by the software watchdog timer or by the nmi input signal to the processor. the nmi event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. ? exceptions. events that occur synchronously to program flow (that is, the exception is taken before the instruction is allowed to complete). conditio ns such as data alignment violations and undefined instructions cause exceptions. ? interrupts. events that occu r asynchronously to program flow. they are caused by in put pins, timers, and other peripherals, as well as by an explicit software instruction. each event type has an associated register to hold the return address and an associated return-from-event instruction. when an event is triggered, the state of the processor is saved on the supervisor stack. the adsp-bf54x blackfin proce ssor event controller consists of two stages, the core event controller (cec) and the system interrupt controller (sic). the co re event controller works with the system interrupt controller to prioritize and control all sys- tem events. conceptually, interru pts from the peripherals enter into the sic and are then routed directly into the general-pur- pose interrupts of the cec. core event controller (cec) the cec supports nine general-purpose interrupts (ivg15C7), in addition to the dedicated interrupt and exception events. of these general-purpose interrupts, the two lowest-priority inter- rupts (ivg15C14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ad sp-bf54x blackfin processors. table 3 describes the inputs to the cec, identifies their names in the event vector table (evt), and lists their priorities. system interrupt controller (sic) the system interrupt controller provides the mapping and rout- ing of events from the many peri pheral interrupt sources to the prioritized general-purpose in terrupt inputs of the cec. although the adsp-bf54x blac kfin processors provide a default mapping, the user can alter the mappings and priorities of interrupt events by writing th e appropriate values into the interrupt assignment registers (sic_iarx). the adsp-bf54x hardware reference manual , system interrupts chapter describes the inputs into the si c and the default mappings into the cec. event control the adsp-bf54x blackfin proce ssors provide the user with a very flexible mechanism to contro l the processing of events. in the cec, three registers are used to coordinate and control events. each register is 16 bits wide: ? cec interrupt latch register (ilat). the ilat register indicates when events have been latched. the appropriate bit is set when the processo r has latched the event and cleared when the even t has been accepted into the system. this register is updated automatically by the controller, but it may be written only when its corresponding imask bit is cleared. ? cec interrupt mask register (imask). the imask regis- ter controls the masking and unmasking of individual events. when a bit is set in the imask register, that event is unmasked and is processed by the cec when asserted. a cleared bit in the imask regist er masks the event, prevent- ing the processor from servicin g the event even though the event may be latched in the ilat register. this register may be read or written while in supervisor mode. note that general-purpose interrupts can be globally en abled and dis- abled with the sti and cli instructions, respectively. ? cec interrupt pending regist er (ipend). the ipend reg- ister keeps track of all nested events. a set bit in the ipend register indicates that the event is currently active or nested at some level. this register is updated automatically by the controller but may be read while in supervisor mode. the sic allows further control of event processing by providing three 32-bit interrupt control and st atus registers. each register contains a bit corresponding to ea ch of the peripheral interrupt events shown in the adsp-bf54x hardware reference manual , system interrupts chapter. table 3. core event controller (cec) priority (0 is highest) event class evt entry 0emulation/test controlemu 1 reset rst 2 nonmaskable interrupt nmi 3exceptionevx 4 reserved 5 hardware error ivhw 6 core timer ivtmr 7 general interrupt 7 ivg7 8 general interrupt 8 ivg8 9 general interrupt 9 ivg9 10 general interrupt 10 ivg10 11 general interrupt 11 ivg11 12 general interrupt 12 ivg12 13 general interrupt 13 ivg13 14 general interrupt 14 ivg14 15 general interrupt 15 ivg15
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 9 of 100 | may 2011 ? sic interrupt mask register s (sic_imaskx). these regis- ters control the masking and unmasking of each peripheral interrupt event. when a bit is set in a register, that periph- eral event is unmasked and is processed by the system when asserted. a cleared bit in the register masks the peripheral event, preventing the processor from servicing the event. ? sic interrupt status regist ers (sic_isrx). as multiple peripherals can be ma pped to a single event, these registers allow the software to determ ine which peripheral event source triggered the interrupt. a set bit indicates the peripheral is asserting the interrupt, and a cleared bit indi- cates the peripheral is not asserting the event. ? sic interrupt wakeup enable registers (sic_iwrx). by enabling the correspo nding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled or in sleep mode when the event is generated. ( for more information, see dynamic power management on page 15. ) because multiple interrupt source s can map to a single general- purpose interrupt, multiple puls e assertions can occur simulta- neously, before or during interrupt processing for an interrupt event already detected on this interrupt input. the ipend reg- ister contents are monitored by the sic as the interrupt acknowledgement. the appropriate ilat register bit is set when an interrupt rising edge is detected. (detection requ ires two core clock cycles.) the bit is cleared when the respective ipend register bit is set. the ipend bit indicates that the event has entered into the proces- sor pipeline. at this point the cec recogn izes and queues the next rising edge event on the corresponding event input. the minimum latency from the rising edge transition of the general- purpose interrupt to the ipend ou tput asserted is three core clock cycles; however, the latency can be much higher, depend- ing on the activity within and the state of the processor. dma controllers adsp-bf54x blackfin processors have multiple, independent dma channels that support automated data transfers with min- imal overhead for the processo r core. dma transfers can occur between the adsp-bf54x proce ssors internal memories and any of the dma-capable peripherals. additionally, dma trans- fers can be accomplished be tween any of the dma-capable peripherals and external device s connected to the external memory interfaces, including ddr and asynchronous memory controllers. while the usb controller and mxvr have their own dedicated dma controllers, the other on-chip peripherals are managed by two centralized dma controllers , called dmac1 (32-bit) and dmac0 (16-bit). both operate in the sclk domain. each dma controller manages 12 independent peripheral dma channels, as well as two independent memory dma streams. the dmac1 controller masters high-bandwidth peripherals over a dedicated 32-bit dma access bu s (dab32). similarly, the dmac0 controller masters most seri al interfaces over the 16-bit dab16 bus. individual dma channels have fixed access prior- ity on the dab buses. dma priori ty of peripherals is managed by a flexible peripheral-to-dm a channel assignment scheme. all four dma contro llers use the same 32-bit dcb bus to exchange data with l1 memory. this includes l1 rom, but excludes scratchpad memory. fine granulation of l1 memory and special dma buffers minimize potential memory conflicts when the l1 memory is accesse d simultaneously by the core. similarly, there are dedicated dma buses between the external bus interface unit (ebiu) and the three dma controllers (dmac1, dmac0, and usb) that arbitrate dma accesses to external memories and the boot rom. the adsp-bf54x blackfin proc essors dma controllers sup- port both 1-dimensional (1d) and 2-dimensional (2d) dma transfers. dma transfer initialization can be implemented from registers or from sets of para meters called descriptor blocks. the 2d dma capability supports arbitrary row and column sizes up to 64k elements by 64k elements, and arbitrary row and column step sizes up to 32k elements. furthermore, the column step size can be less th an the row step size, allowing implementation of interleaved da ta streams. this feature is especially useful in video appl ications where data can be de- interleaved on the fly. examples of dma types support ed by the adsp-bf54x black- fin processors dma controllers include: ? a single, linear buffer that stops upon completion ? a circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer ? 1d or 2d dma using a linked list of descriptors ? 2d dma using an array of desc riptors, specifying only the base dma address wi thin a common page in addition to the dedicated peripheral dma channels, the dmac1 and dmac0 controllers each feature two memory dma channel pairs for transfers between the various memories of the adsp-bf54x blackfin proc essors. this en ables transfers of blocks of data between an y of the memoriesincluding external ddr, rom, sram, and flash memorywith minimal processor intervention. like peripheral dmas, memory dma transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. the memory dma channels of the dmac1 controller (mdma2 and mdma3) can be co ntrolled optionally by the external dma request input pins . when used in conjunction with the external bus interfac e unit (ebiu), this handshaked memory dma (hmdma) scheme ca n be used to efficiently exchange data with block-buffered or fifo-style devices con- nected externally. users can se lect whether the dma request pins control the source or the destination side of the memory dma. it allows control of the number of data transfers for memory dma. the number of transfers per edge is program- mable. this feature can be programmed to allow memory dma to have an increased priority on the external bus relative to the core.
rev. d | page 10 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 host dma port interface the host dma port (hostdp) faci litates a host device external to the adsp-bf54x blackfin processors to be a dma master and transfer data back and forth. the host device always masters the transactions, and the proc essor is always a dma slave device. the hostdp is enabled through the peripheral access bus. once the port has been enabled, the transactions are controlled by the external host. the extern al host programs standard dma configuration words in order to send/receive data to any valid internal or external memory location. the host dma port con- troller includes the following features: ? allows an external master to configure dma read/write data transfers and read port status ? uses a flexible asynchronous memory protocol for its external interface ? allows an 8- or 16-bit external data interface to the host device ? supports half-duplex operation ? supports little/big endian data transfers ? acknowledge mode allows flow control on host transactions ? interrupt mode guarantees a burst of fifo depth host transactions real-time clock the adsp-bf54x blackfin processors real-time clock (rtc) provides a robust set of digital watch features, including current time, stopwatch, and alarm. the rtc is clocked by a 32.768 khz crystal external to the adsp-bf54x blackfin processors. the rtc peripheral has dedicated powe r supply pins so that it can remain powered up and clocked ev en when the rest of the pro- cessor is in a low-power state. the rtc provides several programmable interrupt options, including interrupt per sec- ond, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a pro- grammed alarm time. the 32.768 khz input clock frequency is divided down to a 1 hz signal by a prescaler. the counter function of the timer consists of four counters: a 60-second co unter, a 60-minute counter, a 24-hour counter, and a 32,768-day counter. when enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. there are two alarms. the first alarm is for a time of day. the second alarm is for a day and time of that day. the stopwatch function counts down from a programmed value with one-second reso lution. when the stopwatch is enabled and the counter underflows, an interrupt is generated. like the other peripherals, the rtc can wake up the adsp-bf54x processor from sleep mode upon generation of any rtc wakeup event. additionally, an rtc wakeup event can wake up the adsp-bf54x proces sors from deep sleep mode, and it can wake up the on-chip internal voltage regulator from the hibernate state. connect rtc pins rtxi and rtxo with external components as shown in figure 4 . watchdog timer the adsp-bf54x processors incl ude a 32-bit timer that can be used to implement a software watchdog function. a software watchdog can improve system reli ability by forcing the proces- sor to a known state through generation of a hardware reset, non-maskable interrupt (nmi), or general-purpose interrupt if the timer expires before being reset by software. the program- mer initializes the count value of the timer, enables the appropriate interrupt, and then enables the timer. thereafter, the software must reload the coun ter before it counts to zero from the programmed value. th is protects the system from remaining in an unknown state where software, which would normally reset the timer, has sto pped running due to an external noise condition or software error. if configured to gene rate a hardware reset, the watchdog timer resets both the core and the ad sp-bf54x processors peripher- als. after a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. the timer is clocked by the syst em clock (sclk) at a maximum frequency of f sclk . timers there are up to two timer unit s in the adsp-bf54x blackfin processors. one unit provides eight general-purpose program- mable timers, and the other unit provides three. each timer has an external pin that can be conf igured either as a pulse width modulator (pwm) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and peri- ods of external events. these time rs can be synchronized to an external clock input on the tm rx pins, an external clock tmrclk input pin, or to the internal sclk. figure 4. external components for rtc rtxo c1 c2 x1 suggested components: ecliptek ec38j (through-hole package) epson mc405 12 pf load (surface-mount package) c1 = 22 pf c2 = 22 pf r1 = 10 m note: c1 and c2 are specific to crystal specified for x1. contact crystal manufacturer for details. c1 and c2 specifications assume board trace capacitance of 3 pf. rtxi r1
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 11 of 100 | may 2011 the timer units can be used in conjunction with the four uarts and the can controllers to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. the timers can generate interrup ts to the processor core, pro- viding periodic events for synchronization to either the system clock or to a count of external signals. in addition to the general-purpose programmable timers, another timer is also provided by the processor core. this extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of periodic operating system interrupts. up/down counter and thumbwheel interface a 32-bit up/down counter is provided that can sense the 2-bit quadrature or binary codes typically emitted by industrial drives or manual thumb wheels. the counter can also operate in general-purpose up/down count mo des. then count direction is either controlled by a level-sensitive input pin or by two edge detectors. a third input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. all three pins have a programmable debouncing circuit. an internal signal forwarded to the timer unit enables one timer to measure the intervals between count events. boundary regis- ters enable auto-zero operation or simple system warning by interrupts when programmable count values are exceeded. serial ports (sports) the adsp-bf54x blackfin proce ssors incorporate up to four dual-channel synchronous seri al ports (sport0, sport1, sport2, and sport3) for serial and multiprocessor commu- nications. the sports suppo rt the following features: ?i 2 s capable operation. ? bidirectional operation. each sport has two sets of inde- pendent transmit and receive pins, enabling up to eight channels of i 2 s stereo audio. ? buffered (8-deep) transmit and receive ports. each port has a data register for transferri ng data words to and from other processor components and shift registers for shifting data in and out of the data registers. ? clocking. each transmit and re ceive port can either use an external serial clock or generate its own, in frequencies ranging from (f sclk /131,070) hz to (f sclk /2) hz. ? word length. each sport supports serial data words from 3 to 32 bits in length, transferred most-significant-bit first or least-significant-bit first. ? framing. each transmit and receive port can run with or without frame sync signals for each data word. frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. ? companding in hardware. each sport can perform a-law or -law companding according to itu recommen- dation g.711. companding can be selected on the transmit and/or receive channel of the sport without additional latencies. ?dma operations with single -cycle overhead. each sport can receive and transmit multiple buffers of memory data automatically. the processor can link or chain sequences of dma transfers between a sport and memory. ? interrupts. each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire da ta buffer or buffers through dma. ? multichannel capability. ea ch sport supports 128 chan- nels out of a 1024-channel wind ow and is compatible with the h.100, h.110, mvip-90, and hmvip standards. serial peripheral interface (spi) ports the adsp-bf54x blackfin proce ssors have up to three spi- compatible ports that allow the processor to communicate with multiple spi-compatible devices. each spi port uses three pins for transferring data: two data pins (master output slave input, spixmosi, and master input-slave output, spixmiso) and a clock pin (serial clock, spixsck). an spi chip select input pin (spixss ) lets other spi devices select the processor, and three spi chip select output pins per spi port spixsely let the processor select other spi devices. the spi select pins are reconfigured general-purpose i/o pins. using these pins, the spi ports provide a full-duplex, synchronous serial interface, which support s both master/slave modes and multimaster environments. the spi ports baud rate and clock phase/polarities are pro- grammable, and it has an integrated dma controller, configurable to support transmit or receive data streams. the spis dma controller can only serv ice unidirectional accesses at any given time. the spi ports clock rate is calculated as where the 16-bit spi_baud register contains a value of 2 to 65,535. during transfers, the spi port transmits and receives simultane- ously by serially shifting data in and out on its two serial data lines. the serial clock line sy nchronizes the shifting and sam- pling of data on the two serial data lines. uart ports (uarts) the adsp-bf54x blackfin proce ssors provide up to four full- duplex universal asynchronous receiver/transmitter (uart) ports. each uart port provides a simplified uart interface to other peripherals or hosts, supporting full-duplex, dma-sup- ported, asynchronous transfers of serial data. a uart port spi clock rate f sclk 2 spi_baud ----------------------------------- - =
rev. d | page 12 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 includes support for five to eight data bits, one or two stop bits, and none, even, or od d parity. each uart port supports two modes of operation: ? pio (programmed i/o). the processor sends or receives data by writing or reading i/o-mapped uart registers. the data is double-buffered on both transmit and receive. ? dma (direct memory access). the dma controller trans- fers both transmit and receive data. this reduces the number and frequency of interr upts required to transfer data to and from memory. each uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower default priority than most dma channels because of their relatively low service rates. flexi- ble interrupt timing options ar e available on the transmit side. each uart ports baud rate, seri al data format, error code gen- eration and status, and interrupts are programmable: ? supporting bit rates ranging from (f sclk /1,048,576) to (f sclk ) bits per second. ? supporting data formats from seven to 12 bits per frame. ? both transmit and receive oper ations can be configured to generate maskable interrupts to the processor. the uart ports clock rate is calculated as where the 16-bit uart divisor comes from the uartx_dlh register (most significant 8 bits ) and uartx_dll register (least significant eight bits), and the edbo is a bit in the uartx_gctl register. in conjunction with the general-purpose timer functions, auto- baud detection is supported. uart1 and uart3 feature a pair of uartxrts (request to send) and uartxcts (clear to send) signals for hardware flow purposes. the transmitter hardware is automatically prevented from sending further da ta when the uartxcts input is de- asserted. the receiver can automatically de-assert its uartxrts output when the enhanced receive fifo exceeds a certain high-water level. the capabilities of the uarts are fur- ther extended with support for the infrared data association (irda?) serial infrared physical layer link specification (sir) protocol. controller area network (can) the adsp-bf54x blackfin processors offer up to two can con- trollers that are communication controllers that implement the controller area network (can) 2.0b (active) protocol. this pro- tocol is an asynchronous communications protocol used in both industrial and automotive contro l systems. the can protocol is well suited for control applications due to its capability to com- municate reliably over a network since the protocol incorporates crc checking, messa ge error tracking, and fault node confinement. the adsp-bf54x blackfin processors can controllers offer the following features: ? 32 mailboxes (8 receive only , 8 transmit only, 16 configu- rable for receive or transmit). ? dedicated acceptance masks for each mailbox. ? additional data filtering on first two bytes. ? support for both the standard (11-bit) and extended (29- bit) identifier (i d) message formats. ? support for remote frames. ? active or passive network support. ? can wakeup from hibernation mode (lowest static power consumption mode). ?interrupts, including: tx complete, rx complete, error and global. the electrical characteristics of each network connection are very demanding, so the can interface is typically divided into two parts: a controller and a tran sceiver. this allows a single controller to support different drivers and can networks. the adsp-bf54x blackfin processors can module represents only the controller part of the interface. the controller interface sup- ports connection to 3. 3 v high speed, fault-tolerant, single-wire transceivers. an additional crystal is not required to supply the can clock, as the can clock is derived from the processor system clock (sclk) through a programmable divider. twi controller interface the adsp-bf54x blackfin processo rs include up to two 2-wire interface (twi) modules for providing a simple exchange method of control data between multiple devices. the modules are compatible with the widely used i 2 c bus standard. the twi modules offer the capabilities of simultaneous master and slave operation and support for both 7-bit addressing and multime- dia data arbitration. each twi interface uses two pins for transferring clock (sclx) and data (sdax), and supports the protocol at speeds up to 400k bits/sec. the twi interface pins are compatible with 5 v logic levels. additionally, the adsp-bf54x blackfin processors twi mod- ules are fully compatible with serial camera control bus (sccb) functionality for easier control of various cmos camera sensor devices. ports because of their rich set of peripherals, the adsp-bf54x blackfin processors group the ma ny peripheral signals to ten portsreferred to as port a to port j. most ports contain 16 pins, though some have fewer. ma ny of the associated pins are shared by multiple signals. th e ports function as multiplexer controls. every port has its ow n set of memory-mapped regis- ters to control port muxing and gpio functionality. uart clock rate f sclk 16 1edbo ? () uart_divisor ----------------------------------------------------------------------------- - =
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 13 of 100 | may 2011 general-purpose i/o (gpio) every pin in port a to port j can function as a gpio pin, result- ing in a gpio pin count up to 154. while it is unlikely that all gpio pins will be used in an appl ication, as all pins have multi- ple functions, the richness of gpio functionality guarantees unrestrictive pin usage. every pin that is not used by any func- tion can be configured in gpio mode on an individual basis. after reset, all pins are in gpio mode by default. since neither gpio output nor input drivers ar e active by default, unused pins can be left unconnected. gpio data and direction control registers provide flexible writ e-one-to-set and write-one-to- clear mechanisms so that independent software threads do not need to protect against each ot her because of expensive read- modify-write operations when accessing the same port. pin interrupts every port pin on adsp-bf54x bl ackfin processors can request interrupts in either an edge-sensitive or a level-sensitive manner with programmable polarity. interrupt functionality is decou- pled from gpio operation. four system-level interrupt channels (pint0, pint1, pint2 and pint3) are reserved for this purpose. each of these interrupt channels can manage up to 32 interrupt pins. the assignment from pin to interrupt is not performed on a pin-by-pin basis. rather, groups of eight pins (half ports) can be flexibly a ssigned to interrupt channels. every pin interrupt channel features a special set of 32-bit mem- ory-mapped registers that enab les half-port assignment and interrupt management. this not only includes masking, identi- fication, and clearing of requests , it also enables access to the respective pin states and use of the interrupt latches regardless of whether the interrupt is masked or not. most control registers feature multiple mmr address entries to write-one-to-set or write-one-to-clear them individually. pixel compositor (pixc) the pixel compositor (pixc) provides image overlays with transparent-color support, alpha blending, and color space con- version capabilities for output to tft lcds and ntsc/pal video encoders. it provides all of the control to allow two data streams from two separate da ta buffers to be combined, blended, and converted into appropriate forms for both lcd panels and digital video outputs. the main image buffer pro- vides the basic backgr ound image, which is presented in the data stream. the over lay image buffer allows the user to add multiple foreground text, graphi cs, or video objects on top of the main image or video data stream. enhanced parallel peripheral interface (eppi) the adsp-bf54x blackfin proc essors provide up to three enhanced parallel peripheral inte rfaces (eppis), supporting data widths up to 24 bits. the eppi supports direct connection to tft lcd panels, parallel analog-t o-digital and digital-to-ana- log converters, video encoders and decoders, image sensor modules and other general-purpose peripherals. the following features are supported in the eppi module: ? programmable data length: 8 bi ts, 10 bits, 12 bits, 14 bits, 16 bits, 18 bits, and 24 bits per clock. ? bidirectional and half-duplex port. ? clock can be provided exte rnally or can be generated internally. ? various framed and non-framed operating modes. frame syncs can be generated internally or can be supplied by an external device. ?various general-purpose mode s with zero to three frame syncs for both receive an d transmit directions. ? itu-656 status word error de tection and correction for itu-656 receive modes. ? itu-656 preamble and status word decode. ? three different modes for it u-656 receive modes: active video only, vertical blanking only, and entire field mode. ? horizontal and vertical windowing for gp 2 and 3 frame sync modes. ? optional packing and unpackin g of data to/from 32 bits from/to 8, 16 and 24 bits. if pa cking/unpacking is enabled, endianness can be changed to change the order of pack- ing/unpacking of bytes/words. ? optional sign extension or zero fill for receive modes. ? during receive modes, alternat e even or odd data samples can be filtered out. ? programmable clipping of data values for 8-bit transmit modes. ? rgb888 can be converted to rgb666 or rgb565 for trans- mit modes. ? various de-interleaving/interleaving modes for receiv- ing/transmitting 4:2:2 ycrcb data. ? fifo watermarks and urgent dma features. ? clock gating by an external device assertin g the clock gat- ing control signal. ?configurable lcd data enable (den) output available on frame sync 3. usb on-the-go dual-role device controller the usb otg dual-role device controller (usbdrc) provides a low-cost connectivi ty solution for consumer mobile devices such as cell phones, digital st ill cameras, and mp3 players, allowing these devices to transf er data using a point-to-point usb connection without the need for a pc host. the usbdrc module can operate in a traditional usb peripheral-only mode as well as the host mode presented in the on-the-go (otg) supplement to the usb 2.0 specification. in host mode, the usb module supports transfers at hi gh speed (480 mbps), full speed (12 mbps), and low speed (1.5 mbps) rates. peripheral-only mode supports the high and full speed transfer rates.
rev. d | page 14 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 the usb clock (usb_xi) is prov ided through a dedicated exter- nal crystal or crystal oscillator. see table 62 for related timing requirements. if using a fundam ental mode crystal to provide the usb clock, connect the crystal between usb_xi and usb_xo with a circuit si milar to that shown in figure 7 . use a parallel-resonant, fundamenta l mode, microprocessor-grade crystal. if a third-overtone cr ystal is used, follow the circuit guidelines outlined in clock signals on page 17 for third-over- tone crystals. the usb on-the-go dual-role device controller includes a phase locked loop wi th programmable mult ipliers to generate the necessary internal clocking frequency for usb. the multi- plier value should be programmed based on the usb_xi clock frequency to achieve the necessa ry 480 mhz internal clock for usb high speed operation. for example, for a usb_xi crystal frequency of 24 mhz, the usb_pllosc_ctrl register should be programmed with a multiplier value of 20 to generate a 480 mhz internal clock. ata/atapi-6 interface the atapi interface connects to cd/dvd and hdd drives and is atapi-6 compliant. th e controller implements the peripheral i/o mode, the multi-dma mode, and the ultra dma mode. the dma modes enable faster data transfer and reduced host management. the atapi controller supports pio, multi-dma, and ultra dma atapi accesses. key features include: ? supports pio modes 0, 1, 2, 3, 4 ? supports multiword dma modes 0, 1, 2 ? supports ultra dma modes 0, 1, 2, 3, 4, 5 (up to udma 100) ? programmable timing for ata interface unit ? supports compactflash ca rds using true ide mode by default, the atapi_a0-2 address signals and the atapi_d0-15 data signals are shared on the asynchronous memory interface with the asynchronous memory and nand flash controllers. the data and address signals can be remapped to gpio ports f and g, respectively, by setting portf_mux[1:0] to b#01. keypad interface the keypad interface is a 16-pin interface module that is used to detect the key pressed in a 8 8 (maximum) keypad matrix. the size of the input keypad matrix is programmable. the interface is capable of filtering the boun ce on the input pins, which is common in keypad applications. the width of the filtered bounce is programmable. the modu le is capable of generating an interrupt request to the core once it identifies that any key has been pressed. the interface supports a press-release-press mode and infra- structure for a press-hold mode. the former mode identifies a press, release and press of a key as two consecutive presses of the same key, whereas the latter mode checks the input keys state in periodic intervals to determine the number of times the same key is meant to be pressed. it is possible to detect when multiple keys are pressed simultaneously and to provide limited key reso- lution capability when this happens. secure digital (sd)/sdio controller the sd/sdio controller is a serial interface that stores data at a data rate of up to 10m bytes per second using a 4-bit data line. the sd/sdio controller supports the sd memory mode only. the interface supports all the power modes and performs error checking by crc. code security an otp/security system, consisti ng of a blend of hardware and software, provides cust omers with a flexible and rich set of code security features with lockbox ? secure technology. key features include: ? otp memory ? unique chip id ? code authentication ? secure mode of operation the security scheme is based up on the concept of authentica- tion of digital signatures usin g standards-based algorithms and provides a secure processing environment in which to execute code and protect assets. see lockbox secure technology dis- claimer on page 22 . media transceiver mac layer (mxvr) the adsp-bf549 blackfin proces sors provide a media trans- ceiver (mxvr) mac layer, a llowing the processor to be connected directly to a most ? 1 network through an fot. see figure 5 on page 15 for an example of a mxvr most connection. the mxvr is fully compatible with industry-standard stand- alone most controller devices, supporting 22.579 mbps or 24.576 mbps data transfer. it offers faster lock times, greater jit- ter immunity, and a sophisticated dma scheme for data transfers. the high sp eed internal interface to the core and l1 memory allows the full bandwidth of the network to be utilized. the mxvr can operate as either the network master or as a net- work slave. the mxvr supports synchronous data, asynchronous packets, and control messages using dedicated dma channels that oper- ate autonomously from the proce ssor core moving data to and from l1 and/or l2 memory. sync hronous data is transferred to or from the synchronous data physical channels on the most bus through eight programmabl e dma channels. the synchro- nous data dma channels can operate in various modes including modes that trigger dma operation when data pat- terns are detected in the receive data stream. furthermore, two dma channels support asynchronous traffic, and two others support control message traffic. 1 most is a registered trademark of standard microsystems, corp.
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 15 of 100 | may 2011 interrupts are generated when a user-defined amount of syn- chronous data has been sent or received by the processor or when asynchronous packets or co ntrol messages have been sent or received. the mxvr peripheral can wake up the adsp-bf549 blackfin processor from sleep mode when a wakeup preamble is received over the network or based on any other mxvr interrupt event. additionally, detection of network activity by the mxvr can be used to wake up the adsp-bf 549 blackfin processor from the hibernate state. these features allow the adsp-bf549 processor to operate in a low-power state when there is no network activ- ity or when data is not currently being received or transmitted by the mxvr. the mxvr clock is provided thro ugh a dedicated external crys- tal or crystal oscillator. the freq uency of the external crystal or crystal oscillator can be 256 fs, 384 fs, 512 fs, or 1024 fs for fs = 38 khz, 44.1 khz, or 48 khz. if using a crystal to provide the mxvr clock, use a paralle l-resonant, fundamental mode, microprocessor-grade crystal. dynamic power management the adsp-bf54x blackfin proce ssors provide five operating modes, each with a different performance/power profile. in addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation . control of clocking to each of the adsp-bf54x blackfin processors peripherals also reduces power consumption. see table 4 for a summary of the power settings for each mode. full-on operating modemaximum performance in the full-on mode, the pll is enabled and is not bypassed, providing the capability to run at the maximum operational fre- quency. this is the power-up de fault execution state in which maximum performance can be achieved. the processor core and all enabled peripherals run at full speed. active operating modemoderate power savings in the active mode, the pll is enabled but bypassed. because the pll is bypassed, the processors core clock (cclk) and system clock (sclk) run at the input clock (clkin) frequency. dma access is available to appropri ately configured l1 memories. in the active mode, it is possible to disable the control input to the pll by setting the pll_off bit in the pll control register. this register can be accessed with a user-callable routine in the on-chip rom called bfrom_syscontrol(). for more informa- tion, see the dynamic power management chapter in the adsp-bf54x blackfin proc essor hardware reference . if dis- abled, the pll must be re-enabled before transitioning to the full-on or sleep modes. figure 5. mxvr most connection 600z mlf_m most network audio channels gndmp vddmp most fot txvcc tx_data rx_data status audio dac 27 6 r1 330 6 c1 0.047 m f 0.1 m f 0.01 m f c2 330pf adsp-bf549 mxi mxo mlf_p pg11/ mtxon ph5/mtx ph6/mrx ph7/ mrxon pc1/mmclk mfs pc5/mbclk pc3/tsclk0 pc7/rsclk0 pc4/rfs0 pc2/dt0pri sdata l/rclk bclk mclk 33 6 33 6 33 6 1.25v gnd vddint 1% 2% pps 2% pps 0 6 txgnd 5.0v rxvcc rxgnd 600z 600z 10k 6 24.576mhz xn4114 table 4. power settings mode/state pll pll bypassed core clock (cclk) system clock (sclk) core power full on enabled no enabled enabled on active enabled/ disabled yes enabled enabled on sleep enabled - disabled enabled on deep sleep disabled - disabled disabled on hibernate disabled - disabled disabled off
rev. d | page 16 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 sleep operating modehigh dynamic power savings the sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (cclk). the pll and system clock (sclk), however, continue to operate in this mode. typi- cally an external event or rtc activity will wake up the processor. in the sleep mode, assertion of a wakeup event enabled in the sic_iwrx register causes the processor to sense the value of the bypass bit in the pll control register (pll_ctl). if bypass is disabled , the processor transitions to the full on mode. if bypass is enabled, the processor transi- tions to the active mode. in the sleep mode, system dma access to l1 memory is not supported. deep sleep operating modemaximum dynamic power savings the deep sleep mode maximizes dynamic power savings by dis- abling the clocks to the processor core (cclk) and to all synchronous peripherals (sclk) . asynchronous peripherals, such as the rtc, may still be running but will not be able to access internal resources or external memory. this powered-down mode can only be exited by assertion of the reset interrupt (reset ) or by an asynchrono us interrupt generated by the rtc. in deep sleep mo de, an asynchronous rtc inter- rupt causes the processor to tr ansition to the active mode. assertion of reset while in deep sleep mo de causes the proces- sor to transition to the full on mode. hibernate statemaximum static power savings the hibernate state maximizes stat ic power savings by disabling the voltage and clocks to the processor core (cclk) and to all the synchronous peripherals (sclk). the internal voltage regu- lator for the processor can be shut off by using the bfrom_syscontrol() function in the on-chip rom. this sets the internal power supply voltage (v ddint ) to 0 v to provide the greatest power savings mode. an y critical information stored internally (memory contents, regi ster contents, and so on) must be written to a non-volatile storage device prior to removing power if the processor state is to be preserved. since v ddext is still supplied in this mode, all of the external pins three-state, unless otherwis e specified. this allows other devices that may be connected to the processor to have power still applied without drawing unwanted current. the internal supply regulator can be woken up by can, by the mxvr, by the keypad, by the up /down counter, by the usb, and by some gpio pins. it can also be woken up by a real-time clock wakeup event or by asserting the reset pin. waking up from hibernate state initiates the hardware reset sequence. with the exception of the vr_c tl and the rtc registers, all internal registers and memories lose their content in hibernate state. state variables may be held in external sram or ddr memory. power domains as shown in table 5 , the adsp-bf54x blackfin processors sup- port different power domains. the use of multiple power domains maximizes flexibility while maintaining compliance with industry standard s and conventions. by isolating the inter- nal logic of the adsp-bf54x blac kfin processors into its own power domain separate from th e rtc and other i/o, the pro- cessors can take advantage of dynamic power management without affecting the rtc or other i/o devices. there are no sequencing requirements fo r the various power domains. voltage regulation the adsp-bf54x blackfin processors provide an on-chip volt- age regulator that can generate processor core voltage levels from an external supply (see specifications in operating condi- tions on page 33 ). figure 6 on page 17 shows the typical external components required to complete the power manage- ment system. the regu lator controls the in ternal logic voltage levels and is progra mmable with the voltage regulator control register (vr_ctl) in increments of 50 mv. this register can be accessed using the bfrom_syscontrol() function in the on-chip rom. to reduce standby power consumption, the internal volt- age regulator can be programmed to remove power to the processor core while keeping i/o power supplied. while in hibernate state, v ddext , v ddrtc , v ddddr , v ddusb , and v ddvr can still be applied, eliminating th e need for external buffers. the voltage regulator can be activated from this power-down state by assertion of the reset pin, which then initiates a boot sequence. the regulator can also be disabled and bypassed at the users discretion. for all 600 mh z speed grade models and all automotive grade models, the internal voltage regulator must not be used and v ddvr must be tied to v ddext . for additional information regarding design of the voltage regulator circuit, see switching regulator design considerations for the adsp- bf533 blackfin processors (ee-228) . table 5. power domains power domain vdd range all internal logic, except rtc, ddr, and usb v ddint rtc internal logic and crystal i/o v ddrtc ddr external memory supply v ddddr usb internal logic and crystal i/o v ddusb internal voltage regulator v ddvr mxvr pll and logic v ddmp all other i/o v ddext
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 17 of 100 | may 2011 clock signals the adsp-bf54x blackfin processors can be clocked by an external crystal, a sine wave in put, or a buffered, shaped clock derived from an external clock oscillator. if an external clock is used, it should be a ttl-compatible signal and must not be halted, changed, or operated below the speci- fied frequency during normal operation. this signal is connected to the processors cl kin pin. when an external clock is used, the xtal pin must be left unconnected. alternatively, because the adsp -bf54x blackfin processors include an on-chip oscillator circui t, an external crystal may be used. for fundamental frequenc y operation, use the circuit shown in figure 7 . a parallel-resonant, fundamental frequency, microprocessor-grade crystal is connected across the clkin and xtal pins. the on-chip resistance between clkin and the xtal pin is in the 500 k rang e. typically, further parallel resistors are not recommended. the two capacitors and the series resistor shown in figure 7 fine-tune phase and amplitude of the sine frequency. the 1m ohm pull-up resistor on the xtal pin guarantees that the clock circuit is properly held inac- tive when the processor is in the hibernate state. the capacitor and resist or values shown in figure 7 are typical values only. the capaci tor values are dependent upon the crystal manufacturers load capacitance recommendations and the pcb physical layout. the resistor va lue depends on the drive level specified by the crystal manufa cturer. system designs should verify the customized values based on careful investigations on multiple devices over temperature range. a third-overtone crystal can be used at frequencies above 25 mhz. the circuit is then modified to ensure crystal operation only at the third overtone by ad ding a tuned inductor circuit as shown in figure 7 . a design procedure fo r third-overtone oper- ation is discussed in detail in an application note, using third overtone crystals (ee-168) . the blackfin core runs at a different clock rate than the on-chip peripherals. as shown in figure 8 on page 17 , the core clock (cclk) and system peripheral clock (sclk) are derived from the input clock (clkin) signal. an on-chip pll is capable of multiplying the clkin signal by a programmable 0.5 to 64 multiplication factor (bounded by specified minimum and max- imum vco frequencies). the defaul t multiplier is 8, but it can be modified by a software inst ruction sequence. this sequence is managed by the bfrom_syscontr ol() function in the on-chip rom. on-the-fly cclk and sclk frequency changes can be applied by using the bfrom_syscontrol() function in the on-chip rom. whereas the maximum allowed cclk and sclk rates depend on the applied voltages v ddint and v ddext , the vco is always permitted to run up to the frequency specified by the parts speed grade. the clkout pin reflects the sc lk frequency to the off-chip world. it functions as a referenc e for many timing specifications. while inactive by default, it can be enabled using the ebiu_amgctl register. all on-chip peripherals are clocked by the system clock (sclk). the system clock frequency is programmable by means of the ssel3C0 bits of the pll_div re gister. the values programmed into the ssel fields define a divide ratio between the pll output (vco) and the system clock. sclk divider values are 1 through 15. table 6 illustrates typical system clock ratios. the default ratio is 4. figure 6. voltage regulator circuit v ddvr (low-inductance) v ddint vr out 100f vr out gnd short and low- inductance wire v ddvr + + 100f 10f low esr 100nf setofdecoupling capacitors fds9431a zhcs1000 2.7v to 3.6v input voltage range note: designer should minimize trace length to fds9431a. 10h figure 7. external crystal connections note: for cclk and sclk specifications, see table 15 . figure 8. frequency mo dification methods clkin clkout xtal en clkbuf to pll circuitry frovertone opera o tion only note: values marked with * must be customized depending on the crystal and layout. please analyze carefully. 18 pf* en 18 pf* 700 0 blackfin 0 * v ddext 1m pll 0.5x - 64x 1:15 1, 2, 4, 8 vco clkin dynamic modification requires pll sequencing dynamic modification on-the-fly cclk sclk
rev. d | page 18 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of f sclk . the ssel value can be dynamically changed without any pll lock latencies by writing the appropriate values to the pll divisor register (pll_div) using the bfrom_syscontrol() fu nction in the on-chip rom. the core clock (cclk) freque ncy can also be dynamically changed by means of the csel1C0 bits of the pll_div register. supported cclk divider ratios are 1, 2, 4, and 8, as shown in table 7 . the default ratio is 1. th is programmable core clock capability is useful for fast core frequency modifications. the maximum cclk frequency not only depends on the parts speed grade, it also depends on the applied v ddint voltage. see table 12 on page 34 for details. booting modes the adsp-bf54x blackfin processors have many mechanisms (listed in table 8 ) for automatically loading internal and exter- nal memory after a reset. the boot mode is specified by four bmode input pins dedicated to this purpose. there are two categories of boot modes: mast er and slave. in master boot modes, the processor actively load s data from parallel or serial memories. in slave boot modes, the processor receives data from an external host device. the boot mode s listed in table 8 provide a number of mecha- nisms for automatically loading the processors internal and external memories after a reset. by default, all boot modes use the slowest allowed configuration settings. default settings can be altered via the initialization code feature at boot time or by proper otp programming at pre- boot time. some boot modes require a boot host wait (hwait ) signal, which is a gpio out- put signal that is driven and toggled by the boot kernel at boot time. if pulled high through an external pull-up resistor, the hwait signal behaves active high and will be driven low when the processor is ready for data . conversely, when pulled low, hwait is driven high when th e processor is ready for data. when the boot sequence completes, the hwait pin can be used for other purposes. by default, hwait functionality is on gpio port b (pb11). however, if pb11 is otherwise utilized in the system, an alternate boot host wait (hwaita) signal can be enabled on gpio port h (ph7) by programming the otp_alternate_hwait bit in the pbs00l otp memory page. the bmode pins of the reset configuration register, sampled during power-on resets and so ftware-initiated resets, imple- ment the following modes: ? idle-no boot mode (bmode = 0x0)in this mode, the processor goes into the idle st ate. the idle boot mode helps to recover from illegal operat ing modes, in case the otp memory is misconfigured. ? boot from 8- or 16-bit external flash memory (bmode = 0x1)in this mode, the boot kernel loads the first block header from ad dress 0x2000 0000 and, depend- ing on instructions contained in the header, the boot kernel performs an 8- or 16-bit boot or starts program execution at the address provided by the header. by default, all con- figuration settings are set for the slowest device possible (3- cycle hold time; 15-cycle r/w access times; 4-cycle setup). the ardy pin is not enabled by default. it can, however, be enabled by otp programmin g. similarly, all interface behavior and timings can be customized through otp pro- gramming. this includes activation of burst-mode or page- mode operation. in this mode, all asynchronous interface signals are enabled at the port muxing level. table 6. example system clock ratios signal name ssel3C0 divider ratio vco/sclk example frequency ratios (mhz) vco sclk 0010 2:1 200 100 0110 6:1 300 50 1010 10:1 500 50 table 7. core clock ratios signal name csel1C0 divider ratio vco/cclk example frequency ratios (mhz) vco cclk 00 1:1 300 300 01 2:1 300 150 10 4:1 500 125 11 8:1 200 25 table 8. booting modes bmode3C0 description 0000 idle-no boot 0001 boot from 8- or 16-bit external flash memory 0010 boot from 16-bit asynchronous fifo 0011 boot from serial spi memory (eeprom or flash) 0100 boot from spi host device 0101 boot from serial twi memory (eeprom or flash) 0110 boot from twi host 0111 boot from uart host 1000 reserved 1001 reserved 1010 boot from ddr sd ram/mobile ddr sdram 1011 boot from otp memory 1100 reserved 1101 boot from 8- or 16-bit nand flash memory via nfc 1110 boot from 16-bit host dma 1111 boot from 8-bit host dma table 8. booting modes (continued) bmode3C0 description
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 19 of 100 | may 2011 ? boot from 16-bit asynchrono us fifo (bmode = 0x2)in this mode, the boot kernel starts booting from address 0x2030 0000. every 16-bit word that the boot kernel has to read from the fifo must be requested by a low pulse on the dmar1 pin. ? boot from serial spi memory, eeprom or flash (bmode = 0x3)8-, 16-, 24- or 32-bit addressable devices are supported. the processor uses the pe4 gpio pin to select a single spi eeprom or flash device and uses spi0 to submit a read command an d successive address bytes (0x00) until a valid 8-, 16-, 24- , or 32-bit addressable device is detected. pull-up resistors are required on the spi0sel1 and spi0miso pins. by default, a value of 0x85 is written to the spi0_baud register. ? boot from spi host device (bmode = 0x4)the proces- sor operates in spi slave mode (using spi0) and is configured to receive the bytes of the .ldr file from an spi host (master) agent. the hwait signal must be interro- gated by the host before every transmitted byte. a pull-up resistor is required on the spi0ss input. a pull-down resis- tor on the serial clock (spi0sck) may improve signal quality and boot ing robustness. ? boot from serial twi memory, eeprom or flash (bmode = 0x5)the processor op erates in master mode (using twi0) and selects the tw i slave with the unique id 0xa0. the processor submits su ccessive read commands to the memory device starting at two-byte internal address 0x0000 and begins clocking data into the processor. the twi memory device should comply with philips i 2 c bus specification version 2.1 and have the capability to auto- increment its internal addre ss counter such that the con- tents of the memory device can be read sequentially. by default, a prescale value of 0xa and clkdiv value of 0x0811 is used. unless altere d by otp settings, an i 2 c memory that takes two address bytes is assumed. develop- ment tools ensure that data that is booted to memories that cannot be accessed by the blackfin core is written to an intermediate storage place and then copied to the final des- tination via memory dma. ? boot from twi host (bmode = 0x6)the twi host agent selects the slave with th e unique id 0x5f. the proces- sor (using twi0) replies with an acknowledgement, and the host can then download th e boot stream. the twi host agent should comply with philips i 2 c bus specification ver- sion 2.1. an i 2 c multiplexer can be used to select one processor at a time when booting multiple processors from a single twi. ? boot from uart host (bmode = 0x7)in this mode, the processor uses uart1 as th e booting source. using an autobaud handshake sequence, a boot-stream-formatted program is downloaded by the host. the host agent selects a bit rate within the uarts clocking capabilities. when performing the autobaud , the uart expects an @ (0x40) character (eight data bits, one start bit, one stop bit, no parity bit) on the uart1rx pin to determine the bit rate. it then replies with an acknowledgement, which is composed of four bytes (0xbf, the value of uart1_dll, the value of uart1_dlh, and finally 0x00). the host can then download the boot stre am. the processor deasserts the uart1rts output to hold off the host; uart1cts functionality is not enabled at boot time. ? boot from (ddr) sdram (bmode = 0xa)in this mode, the boot kernel starts booting from address 0x0000 0010. this is a warm boot scenario only. the sdram is expected to contain a valid boot stream and the sdram controller must have been configured by the otp settings. ? boot from 8-bit and 16-bit external nand flash memory (bmode = 0xd)in this mode, auto detection of the nand flash device is performe d. the processor configures portj gpio pins pj1 and pj2 to enable the nd_ce and nd_rb signals, respectively. for correct device operation, pull-up resistors are re quired on both nd_ce (pj1) and nd_rb (pj2) signals. by default, a value of 0x0033 is writ- ten to the nfc_ctl regist er. the booting procedure always starts by booting from byte 0 of block 0 of the nand flash device. in this boot mode, the hwait signal does not toggle. the respective gpio pin remains in the high-impedance state. nand flash boot supports the following features: ? device auto detection ? error detection and correction for maximum reliability ? no boot stream size limitation ? peripheral dma via channel 22, providing efficient transfer of all data (excluding the ecc parity data) ? software-configurable boot mode for booting from boot streams expa nding multiple blocks, including bad blocks ? software-configurable boot mode for booting from multiple copies of the boot stream allowing for han- dling of bad blocks and uncorrectable errors ? configurable timing via otp memory small page nand flash device s must have a 512-byte page size, 32 pages per block, a 16-byte spare area size and a bus configuration of eight bits. by default, all read requests from the nand flash are follo wed by four ad dress cycles. if the nand flash device re quires only three address cycles, then the device must be capable of ignoring the additional address cycle. the small page nand flash device must comply with the following command set: reset: 0xff read lower half of page: 0x00 read upper half of page: 0x01 read spare area: 0x50
rev. d | page 20 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 for large page nand flash devices, the 4-byte electronic signature is read in order to configure the kernel for boot- ing. this allows support for multiple large page devices. the fourth byte of the electr onic signature must comply with the specifications in table 9 . any configuration from table 9 that also complies with the command set listed below is di rectly supported by the boot kernel. there are no restrictions on the page size or block size as imposed by the small-page boot kernel. large page devices must suppo rt the following command set: large page devices must not support or react to nand flash command 0x50. this is a small page nand flash command used for device auto detection. by default, the boot kernel will always issue five address cycles; therefore, if a large page device requires only four cycles, the device must be capable of ignoring the additional address cycle. 16-bit nand flash memory devices must only support the issu- ing of command and address cycles via the lower eight bits of the data bus. devices that use the full 16-bit bus for command and address cycles are not supported. ? boot from otp memory (bmode = 0xb)this provides a standalone booting method. the boot stream is loaded from on-chip otp memory. by de fault, the boot stream is expected to start from otp pa ge 0x40 and can occupy all public otp memory up to pa ge 0xdf (2560 bytes). since the start page is programmable, the maximum size of the boot stream can be extended to 3072 bytes. ? boot from 16-bit host dm a (bmode = 0xe)in this mode, the host dma port is configured in 16-bit acknowl- edge mode with little endian data format. unlike other modes, the host is responsible for interpreting the boot stream. it writes data blocks individually into the host dma port. before configurin g the dma settings for each block, the host may either poll the allow_config bit in host_status or wait to be interrupted by the hwait signal. when using hwait, the host must still check allow_config at least once before beginning to con- figure the host dma port. after completing the configuration, the host is requ ired to poll the ready bit in host_status before beginnin g to transfer data. when the host sends an hirq contro l command, the boot kernel issues a call instruction to address 0xffa0 0000. it is the hosts responsibility to ensure valid code has been placed at this address. the routine at address 0xffa0 0000 can be a simple initialization routine to configure internal resources, such as the sdram controller, which then returns using an rts instruction. the routine may also be the final application, which will never return to the boot kernel. ? boot from 8-bit host dma (bmode = 0xf)in this mode, the host dma port is configured in 8-bit interrupt mode with little endian data format. unlike other modes, the host is responsible for inte rpreting the boot stream. it writes data blocks individu ally to the host dma port. before configuring the dma se ttings for each block, the host may either poll th e allow_config bit in host_status or wait to be interrupted by the hwait signal. when using hwait, the host must still check allow_config at least once before beginning to con- figure the host dma port. the host will receive an interrupt from the host_ack signal every time it is allowed to send the next fifo depths worth (sixteen 32-bit words) of information. when the host sends an hirq con- trol command, the boot kernel issues a call instruction to address 0xffa0 0000. it is th e host's responsibility to ensure valid code has been plac ed at this address. the rou- tine at address 0xffa0 0000 ca n be a simple initialization routine to configure internal resources, such as the sdram controller, which then returns using an rts instruction. the routine may also be the final application, which will never return to the boot kernel. for each of the boot modes, a 16-byte header is first read from an external memory device. the header specifies the number of bytes to be transferred and th e memory destination address. multiple memory blocks may be loaded by any boot sequence. once all blocks are loaded, pr ogram execution commences from the address stored in the evt1 register. prior to booting, the pre-boot routine interrogates the otp memory. individual boot modes can be customized or disabled based on otp programming. ex ternal hardware, especially booting hosts, may monitor th e hwait signal to determine table 9. byte 4 electronic signature specification page size (excluding spare area) d1:d0 00 1k bytes 01 2k bytes 10 4k bytes 11 8k bytes spare area size d2 0 8 bytes/512 bytes 1 16 bytes/512 bytes block size (excluding spare area) d5:4 00 64k bytes 01 128k bytes 10 256k bytes 11 512k bytes bus width d6 0 x8 1x16 not used for configuration d3, d7 reset: 0xff read electronic signature: 0x90 read: 0x00, 0x30 (confirm command)
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 21 of 100 | may 2011 when the pre-boot has finished and the boot kernel starts the boot process. however, the hw ait signal does not toggle in nand boot mode. by programming otp memory, the user can instruct the preboo t routine to also customize the pll, volt- age regulator, ddr controller, and/or asynchronous memory interface controller. the boot kernel differentiates be tween a regular hardware reset and a wakeup-from-hibernate even t to speed up booting in the later case. bits 6-4 in the syst em reset configuration (syscr) register can be used to bypass the pre-boot routine and/or boot kernel in case of a software reset. they can also be used to simu- late a wakeup-from-hibernate boot in the software reset case. the boot process can be further customized by initialization code. this is a piece of code that is loaded and executed prior to the regular application boot. typically, this is used to configure the ddr controller or to speed up booting by managing pll, clock frequencies, wait stat es, and/or serial bit rates. the boot rom also features c-ca llable function entries that can be called by the user application at run time. this enables sec- ond-stage boot or booting management schemes to be implemented with ease. instruction set description the blackfin processor family a ssembly language instruction set employs an algebraic syntax desi gned for ease of coding and readability. the instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to a very small final memory size. th e instruction set also provides fully featured multifunction instructions that allow the pro- grammer to use many of the proce ssor core resources in a single instruction. coupled with many features more often seen on microcontrollers, this instruction set is very efficient when com- piling c and c++ source code. in addition, the architecture supports both user (algorithm/app lication code) and supervisor (o/s kernel, device drivers, debuggers, isrs) modes of opera- tion, allowing multiple levels of access to core processor resources. the assembly language, which takes advantage of the proces- sors unique architecture, offe rs the following advantages: ? seamlessly integrated dsp/mcu features are optimized for both 8-bit and 16-bit operations. ? a multi-issue load/store modified-harvard architecture, which supports two 16-bit mac or four 8-bit alu + two load/store + two pointer updates per cycle. ? all registers, i/o, and memory are mapped into a unified 4g byte memory space, providing a simplified program- ming model. ? microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and ex traction; integer operations on 8-, 16-, and 32-bit data-typ es; and separate user and supervisor stack pointers. ? code density enhancements, wh ich include intermixing of 16- and 32-bit instructions (n o mode switching, no code segregation). frequently used instructions are encoded in 16 bits. development tools the adsp-bf54x blackfin proc essors are supported with a complete set of crosscore? software and hardware develop- ment tools, including anal og devices emulators and visualdsp++? development envi ronment. the same emulator hardware that supports other bl ackfin processors also fully emulates the adsp-bf54x blackfin processors. ez-kit lite evaluation board for evaluation of adsp-bf54x blackfin processors, use the adsp-bf548 ez-kit lite ? board available from analog devices. order part number adzs-bf548-ezlite. the board comes with on-chip emulation ca pabilities and is equipped to enable software development. multiple daughter cards are available. designing an emulator-compatible processor board the analog devices family of em ulators are tools that every sys- tem developer needs to test and debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag processor. the emulator uses the tap to access the internal fe atures of the processor, allow- ing the developer to load co de, set breakpoints, observe variables, observe memory, and examine registers. the proces- sor must be halted to send da ta and commands, but once an operation has been completed by the emulator, the processor is set running at full speed with no impact on system timing. to use these emulators, the target board must include a header that connects the processors jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor conne ctions, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see analog devices jtag emul ation technical reference (ee-68) on the analog devices web site under www.analog.com/ee-notes . this document is updated regularly to keep pace with improvements to emulator support. mxvr board layout guidelines the mxvr loop filter rc network is connected between the mlf_p and mlf_m pins in the following manner: capacitors: ? c1: 0.047 f (pps type, 2% tolerance recommended) ? c2: 330 pf (pps type, 2% tolerance recommended) resistor: ? r1: 330 (1% tolerance) the rc network should be loca ted physically close to the mlf_p and mlf_m pins on the board. the rc network should be shielded using gnd mp traces. avoid routing other switching si gnals near the rc network to avoid crosstalk.
rev. d | page 22 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 mxi driven with extern al clock oscillator ic: ? mxi should be driven with the clock output of a clock oscillator ic running at a frequency of 49.152 mhz or 45.1584 mhz. ? mxo should be left unconnected. ? avoid routing other switching signals near the oscillator and clock output trace to avoid crosstalk. when not possi- ble, shield traces with ground. mxi/mxo with external crystal: ? the crystal must be a fundamental mode crystal running at a frequency of 49.152 mhz or 45.1584 mhz. ? the crystal and load capacitors should be placed physically close to the mxi and mxo pins on the board. ? board trace capacitance on each lead should not be more than 3 pf. ? trace capacitance plus load capacitance shou ld equal the load capacitance specification for the crystal. ? avoid routing other switching signals near the crystal and components to avoid crosstalk. when not possible, shield traces and components with ground. v ddmp /gnd mp mxvr pll power domain: ?route v ddmp and gnd mp with wide traces or as isolated power planes. ?drive v ddmp to same level as v ddint . ? place a ferrite bead between the v ddint power plane and the v ddmp pin for noise isolation. ? locally bypass v ddmp with 0.1 f and 0.01 f decoupling capacitors to gnd mp . ? avoid routing switchin g signals near to v ddmp and gnd mp traces to avoid crosstalk. fiber optic transceiver (fot) connections: ? keep the traces between th e adsp-bf549 processor and the fot as short as possible. ? the receive data trace connecting the fot receive data output pin to the adsp-bf549 ph6/mrx input pin should have a 0 series termination resistor placed close to the fot receive data output pin. typically, the edge rate of the fot receive data signal driven by the fot is very slow, and further degradation of the edge rate is not desirable. ? the transmit data trace connecting the adsp-bf549 ph5/mtx output pin to the fot transmit data input pin should have a 27 series term ination resistor placed close to the adsp-bf549 ph5/mtx pin. ? the receive data trace and th e transmit data trace between the adsp-bf549 processor and the fot should not be routed close to each other in parallel over long distances to avoid crosstalk. related documents the following publications that describe the adsp-bf54x blackfin processors (and related processors) can be ordered from any analog devices sales of fice or accessed electronically on www.analog.com: ? adsp-bf54x blackfin processo r hardware reference, vol- ume 1 and volume 2 ? blackfin processor programming reference ? adsp-bf542/bf544/b f547/bf548/bf549 blackfin anomaly list related signal chains a signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the "signal chain" entry in wikipedia or the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal processing comp onents that are designed to work together well. a tool fo r viewing relationships between specific applications and related components is available on the www.analog.com website. the application signal chains page in the circuits from the lab tm site ( http://www.analog.com/circuits ) provides: ? graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying be st practice design techniques lockbox secure technology disclaimer analog devices products contai ning lockbox secure technol- ogy are warranted by analog devi ces as detailed in the analog devices standard terms and conditions of sale. to our knowl- edge, the lockbox secure technolo gy, when used in accordance with the data sheet and hardwa re reference manual specifica- tions, provides a secure method of implementing code and data safeguards. however, analog devices does not guarantee that this technology provides abso lute security. accordingly, analog devices hereby disclaims any and all express and implied warr anties that the lock- box secure technology cannot be breached, compromised, or otherwise circumvented and in no event shall analog devices be liable for any loss, damage, destruction, or release of data, information, physic al property, or intel- lectual property.
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 23 of 100 | may 2011 pin descriptions the adsp-bf54x processor pin multiplexing scheme is shown in table 10 . table 10. pin multiplexing primary pin function (number of pins) 1, 2 first peripheral function second peripheral function third peripheral function fourth peripheral function interrupt capability port a gpio (16 pins) sport2 (8 pins) tmr4 (1 pin) taci7 (1 pin) taclk7C0 (8 pins) interrupts (16 pins) tmr5 (1 pin) sport3 (8 pins) tmr6 (1 pin) tmr7 (1 pin) port b gpio (15 pins) twi1 (2 pins) uart2 or 3 ctl (2 pins) uart2 (2 pins) uart3 (2 pins) taci2-3 (2 pins) interrupts (15 pins) spi2 sel1-3 (3 pins) tmr0C2 (3 pins) spi2 (3 pins) tmr3 (1 pin) hwait (1 pin) port c gpio (16 pins) sport0 (8 pins) mxvr mmclk, mbclk (2 pins) interrupts (8 pins) 3 sdh (6 pins) interrupts (8 pins) port d gpio (16 pins) ppi1 d0C15 (16 pins) host d0C15 (16 pins) s port1 (8 pins) ppi0 d18C 23 (6 pins) interrupts (8 pins) ppi2 d0C7 (8 pins) keypad row 0C3 col 0C3 (8 pins) interrupts (8 pins) port e gpio (16 pins) spi0 (7 pins) keypad row 4C6 col 4C7 (7 pins) taci0 (1 pin) interrupts (8 pins) uart0 tx (1 pin) keypad r7 (1 pin) uart0 rx (1 pin) uart0 or 1 ctl (2 pins) interrupts (8 pins) ppi1 clk,fs (3 pins) twi0 (2 pins) port f gpio (16 pins) ppi0 d0C15 (16 pins) atapi d0-15a interrupts (8 pins) interrupts (8 pins) port g gpio (16 pins) ppi0 clk,fs (3 pins) data 16C17 (2 pins) tmrclk (1 pin) interrupts (8 pins) atapi a0-2a spi1 sel1C3 (3 pins) host ctl (3 pins) ppi 2 clk,fs (3 pins) czm (1 pin) spi1 (4 pins) mxvr mtxon (1 pin) taci4-5 (2 pins) interrupts (8 pins) can0 (2 pins) can1 (2 pins)
rev. d | page 24 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 pin definitions for the adsp-bf 54x processors are listed in table 11 . in order to maintain ma ximum function and reduce package size and ball count, some balls have dual, multiplexed functions. in cases where ball function is reconfigurable, the default state is shown in plain text, while the alternate function is shown in italics. all pins are three-stated during and immediately after reset, with the exception of the external memory interface, asynchro- nous and synchronous memory control, and the buffered xtal output pin (clkbuf). on the external memory interface, the control and address lines are driv en high, with the exception of clkout, which toggles at the sy stem clock rate. during hiber- nate, all outputs are three-stat ed unless otherwise noted in table 11 . all i/o pins have their input buffers disabled with the exception of the pins that need pull-ups or pull-downs, as noted in table 11 . it is strongly advised to use the available ibis models to ensure that a given board design meet s overshoot/unde rshoot and sig- nal integrity requirements. additionally, adding a paralle l termination to clkout may prove useful in further enhancing signal integrity. be sure to verify overshoot/undershoot and signal integrity specifications on actual hardware. port h gpio (14 pins) uart1 (2 pins) ppi0-1_fs3 (2 pins) taci1 (1 pin) interrupts (8 pins) atapi_reset (1 pin) tmr8 (1 pin) ppi2_fs3 (1 pin) host_addr (1 pin) tmr9 (1 pin) counter down/gate (1 pin) host_ack (1 pin) tmr10 (1 pin) counter up/dir (1 pin) mxvr mrx, mtx, mrxon /gpw (3 pins) 4 dmar 0C1 (2 pins) taci8C10 (3 pins) taclk8C10 (3 pins) hwaita amc addr 4-9 (6 pins ) interrupts (6 pins) port i gpio (16 pins) async addr10C25 (16 pins) interrupts (8 pins) interrupts (8 pins) port j gpio (14 pins) async ctl and misc interrupts (8 pins) interrupts (6 pins) 1 port connections may be inputs or outputs after power up depending on the model and boot mode chosen. 2 all port connections always power up as inputs for some period of time and require resistive termination to a safe condition if used as outputs in the system. 3 a total of 32 interrupts at once are available from ports c through j, configurable in byte-wide blocks. 4 gpw functionality available when mxvr is not present or unused. table 10. pin multiplexing (continued) primary pin function (number of pins) 1, 2 first peripheral function second peripheral function third peripheral function fourth peripheral function interrupt capability
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 25 of 100 | may 2011 table 11. pin descriptions pin name i/o 1 function (first/second/third/fourth) driver type 2 port a: gpio/ sport2C3 / tmr4C7 pa0/ tfs2 i/o gpio/ sport2 transmit frame sync c pa1/ dt2sec / tmr4 i/o gpio/ sport2 transmit data secondary / timer 4 c pa2/ dt2pri i/o gpio/ sport2 transmit data primary c pa3/ tsclk2 i/o gpio/ sport2 transmit serial clock a pa4/ rfs2 i/o gpio/ sport2 receive frame sync c pa5/ dr2sec/tmr5 i/o gpio/ sport2 receive data secondary / timer 5 c pa6/ dr2pri i/o gpio/ sport2 receive data primary c pa7/ rsclk2 / taclk0 i/o gpio/ sport2 receive serial clock / alternate input clock 0 a pa8/ tfs3 / taclk1 i/o gpio/ sport3 transmit frame sync / alternate input clock 1 c pa9/ dt3sec / tmr6 i/o gpio/ sport3 transmit data secondary / timer 6 c pa10/ dt3pri / taclk2 i/o gpio/ sport3 transmit data primary / alternate input clock 2 c pa11/ tsclk3 / taclk3 i/o gpio/ sport3 transmit serial clock / alternate input clock 3 a pa12/ rfs3 / taclk4 i/o gpio/ sport3 receive frame sync / alternate input clock 4 c pa13/ dr3sec/tmr7 / taclk5 i/o gpio/ sport3 receive data secondary / timer 7 / alternate input clock 5 c pa14/ dr3pri / taclk6 i/o gpio/ sport3 receive data primary / alternate input clock 6 c pa15/ rsclk3 / taclk7 and taci7 i/o gpio/ sport3 receive serial clock / alt input clock 7 and alt capture input 7 a port b: gpio/ twi1 / uart2C3 / spi2 / tmr0C3 pb0/ scl1 i/o gpio/ twi1 serial clock (open-drain output: requires a pull-up resistor.) e pb1/ sda1 i/o gpio/ twi1 serial data (open-drain output: requires a pull-up resistor.) e pb2/ uart3rts i/o gpio/ uart3 request to send c pb3/ uart3cts i/o gpio/ uart3 clear to send a pb4/ uart2tx i/o gpio/ uart2 transmit a pb5/ uart2rx / taci2 i/o gpio/ uart2 receive / alternate capture input 2 a pb6/ uart3tx i/o gpio/ uart3 transmit a pb7/ uart3rx / taci3 i/o gpio/ uart3 receive / alternate capture input 3 a pb8/ spi2ss / tmr0 i/o gpio/ spi2 slave select input / timer 0 a pb9/ spi2sel1 / tmr1 i/o gpio/ spi2 slave select enable 1 / timer 1 a pb10 spi2sel2 / tmr2 i/o gpio/ spi2 slave select enable 2 / timer 2 a pb11/ spi2sel3 / tmr3/ hwait i/o gpio/ spi2 slave select enable 3 / timer 3 / boot host wait a pb12/ spi2sck i/o gpio/ spi2 clock a pb13/ spi2mosi i/o gpio/ spi2 master out slave in c pb14/ spi2miso i/o gpio/ spi2 master in slave out c
rev. d | page 26 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 port c: gpio/ sport0 / sd controller / mxvr (most) pc0/ tfs0 i/o gpio/ sport0 transmit frame sync c pc1/ dt0sec / mmclk i/o gpio/ sport0 transmit data secondary / mxvr master clock c pc2/ dt0pri i/o gpio/ sport0 transmit data primary c pc3/ tsclk0 i/o gpio/ sport0 transmit serial clock a pc4/ rfs0 i/o gpio/ sport0 receive frame sync c pc5/ dr0sec/mbclk i/o gpio/ sport0 receive data secondary / mxvr bit clock c pc6/ dr0pri i/o gpio/ sport0 receive data primary c pc7/ rsclk0 i/o gpio/ sport0 receive serial clock c pc8/ sd_d0 i/o gpio/ sd data bus a pc9/ sd_d1 i/o gpio/ sd data bus a pc10/ sd_d2 i/o gpio/ sd data bus a pc11/ sd_d3 i/o gpio/ sd data bus a pc12/ sd_clk i/o gpio/ sd clock output a pc13/ sd_cmd i/o gpio/ sd command a port d: gpio/ ppi0C2 / sport 1 / keypad / host dma pd0/ ppi1_d0 / host_d8 / tfs1 / ppi0_d18 i/o gpio/ ppi1 data / host dma / sport1 transmit frame sync / ppi0 data c pd1/ ppi1_d1 / host_d9 / dt1sec / ppi0_d19 i/o gpio/ ppi1 data / host dma / sport1 transmit data secondary / ppi0 data c pd2/ ppi1_d2 / host_d10 / dt1pri / ppi0_d20 i/o gpio/ ppi1 data / host dma / sport1 transmit data primary / ppi0 data c pd3/ ppi1_d3 / host_d11 / tsclk1 / ppi0_d21 i/o gpio/ ppi1 data / host dma / sport1 transmit serial clock / ppi0 data a pd4/ ppi1_d4 / host_d12 / rfs1 / ppi0_d22 i/o gpio/ ppi1 data / host dma / sport1 receive frame sync / ppi0 data c pd5/ ppi1_d5 / host_d13 / dr1sec / ppi0_d23 i/o gpio/ ppi1 data / host dma / sport1 receive data secondary / ppi0 data c pd6/ ppi1_d6 / host_d14 / dr1pri i/o gpio/ ppi1 data / host dma / sport1 receive data primary c pd7/ ppi1_d7 / host_d15 / rsclk1 i/o gpio/ ppi1 data / host dma / sport1 receive serial clock a pd8/ ppi1_d8 / host_d0 / ppi2_d0 / key_row0 i/o gpio/ ppi1 data / host dma / ppi2 data / keypad row input a pd9/ ppi1_d9 / host_d1 / ppi2_d1 / key_row1 i/o gpio/ ppi1 data / host dma / ppi2 data / keypad row input a pd10/ ppi1_d10 / host_d2 / ppi2_d2 / key_row2 i/o gpio/ ppi1 data / host dma / ppi2 data / keypad row input a pd11/ ppi1_d11 / host_d3 / ppi2_d3 / key_row3 i/o gpio/ ppi1 data / host dma / ppi2 data / keypad row input a pd12/ ppi1_d12 / host_d4 / ppi2_d4 / key_col0 i/o gpio/ ppi1 data / host dma / ppi2 data / keypad column output a pd13/ ppi1_d13 / host_d5 / ppi2_d5 / key_col1 i/o gpio/ ppi1 data / host dma / ppi2 data / keypad column output a pd14/ ppi1_d14 / host_d6 / ppi2_d6 / key_col2 i/o gpio/ ppi1 data / host dma / ppi2 data / keypad column output a pd15/ ppi1_d15 / host_d7 / ppi2_d7 / key_col3 i/o gpio/ ppi1 data / host dma / ppi2 data / keypad column output a table 11. pin descriptions (continued) pin name i/o 1 function (first/second/third/fourth) driver type 2
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 27 of 100 | may 2011 port e: gpio/ spi0 / uart0-1 / ppi1 / twi0 / keypad pe0/ spi0sck / key_col7 3 i/o gpio/ spi0 clock / keypad column output a pe1/ spi0miso / key_row6 3 i/o gpio/ spi0 master in slave out / keypad row input c pe2/ spi0mosi / key_col6 i/o gpio/ spi0 master out slave in / keypad column output c pe3/ spi0ss / key_row5 i/o gpio/ spi0 slave select input / keypad row input a pe4/ spi0sel1 / key_col 3 i/o gpio/ spi0 slave select enable 1 / keypad column output a pe5/ spi0sel2 / key_row4 i/o gpio/ spi0 slave select enable 2 / keypad row input a pe6/ spi0sel3 / key_col4 i/o gpio/ spi0 slave select enable 3 / keypad column output a pe7/ uart0tx / key_row7 i/o gpio/ uart0 transmit / keypad row input a pe8/ uart0rx / taci0 i/o gpio/ uart0 receive / alternate capture input 0 a pe9/ uart1rts i/o gpio/ uart1 request to send a pe10/ uart1cts i/o gpio/ uart1 clear to send a pe11/ ppi1_clk i/o gpio / ppi1clock a pe12/ ppi1_fs1 i/o gpio/ ppi1 frame sync 1 a pe13/ ppi1_fs2 i/o gpio/ ppi1 frame sync 2 a pe14/ scl0 i/o gpio/ twi0 serial clock (open-drain output: requires a pull-up resistor.) e pe15/ sda0 i/o gpio/ twi0 serial data (open-drain output: requires a pull-up resistor.) e port f: gpio/ppi0/alternate atapi data pf0/ ppi0_d0/atapi_d0a i/o gpio/ ppi0 data/alternate atapi data a pf1/ ppi0_d1/atapi_d1a i/o gpio/ ppi0 data / alternate atapi data a pf2/ ppi0_d2/atapi_d2a i/o gpio/ ppi0 data / alternate atapi data a pf3/ ppi0_d3/atapi_d3a i/o gpio/ ppi0 data / alternate atapi data a pf4/ ppi0_d4/atapi_d4a i/o gpio/ ppi0 data / alternate atapi data a pf5/ ppi0_d5/atapi_d5a i/o gpio/ ppi0 data / alternate atapi data a pf6/ ppi0_d6/atapi_d6a i/o gpio/ ppi0 data / alternate atapi data a pf7/ ppi0_d7/atapi_d7a i/o gpio/ ppi0 data / alternate atapi data a pf8/ ppi0_d8/atapi_d8a i/o gpio/ ppi0 data / alternate atapi data a pf9/ ppi0_d9/atapi_d9a i/o gpio/ ppi0 data / alternate atapi data a pf10/ ppi0_d10/atapi_d10a i/o gpio/ ppi0 data / alternate atapi data a pf11/ ppi0_d11/atapi_d11a i/o gpio/ ppi0 data / alternate atapi data a pf12/ ppi0_d12/atapi_d12a i/o gpio/ ppi0 data/alternate atapi data a pf13/ ppi0_d13/atapi_d13a i/o gpio/ ppi0 data / alternate atapi data a pf14/ ppi0_d14/atapi_d14a i/o gpio/ ppi0 data / alternate atapi data a pf15/ ppi0_d15/atapi_d15a i/o gpio/ ppi0 data / alternate atapi data a table 11. pin descriptions (continued) pin name i/o 1 function (first/second/third/fourth) driver type 2
rev. d | page 28 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 port g: gpio/ ppi0 / spi1 / ppi2 / up-down counter / can0C1 / host dma / mxvr (most)/atapi pg0/ ppi0_clk / tmrclk i/o gpio/ ppi0 clock / external timer reference a pg1/ ppi0_fs1 i/o gpio/ ppi0 frame sync 1 a pg2/ ppi0_fs2 / atapi_a0a i/o gpio/ ppi0 frame sync 2 / alternate atapi address a pg3/ ppi0_d16 / atapi_a1a i/o gpio/ ppi0 data / alternate atapi address a pg4/ ppi0_d17 / atapi_a2a i/o gpio/ ppi0 data / alternate atapi address a pg5/ spi1sel1 / host_ce / ppi2_fs2 / czm i/o gpio/ spi1 slave select / host dma chip enable / ppi2 frame sync 2 / counter zero marker a pg6/ spi1sel2 / host_rd / ppi2_fs1 i/o gpio/ spi1 slave select / host dma read / ppi2 frame sync 1a pg7/ spi1sel3 / host_wr / ppi2_clk i/o gpio/ spi1 slave select / host dma write / ppi2 clock a pg8/ spi1sck i/o gpio/ spi1 clock c pg9/ spi1miso i/o gpio/ spi1 master in slave out c pg10/ spi1mosi i/o gpio/ spi1 master out slave in c pg11/ spi1ss /mtxon i/o gpio/ spi1 slave select input / mxvr transmit phy on a pg12/ can0tx i/o gpio/ can0 transmit a pg13/ can0rx / taci4 i/o gpio/ can0 receive / alternate capture input 4 a pg14/ can1tx i/o gpio/ can1 transmit a pg15/ can1rx / taci5 i/o gpio/ can1 receive / alternate capture input 5 a port h: gpio/ amc / extdma / uart1 / ppi0C2 / atapi / up- down counter / tmr8-10 / host dma / mxvr (most) ph0/ uart1tx / ppi1_fs3_den i/o gpio/ uart1 transmit / ppi1 frame sync 3a ph1/ uart1rx / ppi0_fs3_den / taci1 i/o gpio/ uart 1 receive / ppi0 frame sync 3/ alternate capture input 1 a ph2/ atapi_reset / tmr8 / ppi2_fs3_den i/o gpio/ atapi interface hard reset signal / timer 8 / ppi2 frame sync 3a ph3/ host_addr / tmr9 / cdg i/o gpio/ host address / timer 9 / count down and gate a ph4/ host_ack / tmr10 / cud i/o gpio/ host acknowledge / timer 10 / count up and direction a ph5/ mtx / dmar0 / taci8 and taclk8 i/o gpio/ mxvr transmit data / ext. dma request / alt capt. in. 8 /alt in. clk 8 c ph6/ mrx / dmar1 / taci9 and taclk9 i/o gpio/ mxvr receive data / ext. dma request / alt capt. in. 9 /alt in. clk 9 a ph7/ mrxon /gpw / taci10 and taclk10 / hwaita 4,5 i/o gpio/ mxvr receive phy on / alt capt. in. 10 /alt in. clk 10 / alternate boot host wait a ph8/ a4 6 i/o gpio/ address bus for async access a ph9/ a5 6 i/o gpio/ address bus for async access a ph10/ a6 6 i/o gpio/ address bus for async access a ph11/ a7 6 i/o gpio/ address bus for async access a ph12/ a8 6 i/o gpio/ address bus for async access a ph13/ a9 6 i/o gpio/ address bus for async access a table 11. pin descriptions (continued) pin name i/o 1 function (first/second/third/fourth) driver type 2
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 29 of 100 | may 2011 port i: gpio/ amc pi0/ a10 6 i/o gpio/ address bus for async access a pi1/ a11 6 i/o gpio/ address bus for async access a pi2/ a12 6 i/o gpio/ address bus for async access a pi3/ a13 6 i/o gpio/ address bus for async access a pi4/ a14 6 i/o gpio/ address bus for async access a pi5/ a15 6 i/o gpio/ address bus for async access a pi6/ a16 6 i/o gpio/ address bus for async access a pi7/ a17 6 i/o gpio/ address bus for async access a pi8/ a18 6 i/o gpio/ address bus for async access a pi9/ a19 6 i/o gpio/ address bus for async access a pi10/ a20 6 i/o gpio/ address bus for async access a pi11/ a21 6 i/o gpio/ address bus for async access a pi12/ a22 6 i/o gpio/ address bus for async access a pi13/ a23 6 i/o gpio/ address bus for async access a pi14/ a24 6 i/o gpio/ address bus for async access a pi15/ a25 / nr_clk 6 i/o gpio/ address bus for async access/ nor clock a port j: gpio/ amc / atapi pj0 / ardy / wait i/o gpio/ async ready/nor wait a pj1 / nd_ce 7 i/o gpio/ nand chip enable a pj2 / nd_rb i/o gpio/ nand ready busy a pj3 / atapi_dior i/o gpio/ atapi read a pj4 / atapi_diow i/o gpio/ atapi write a pj5 / atapi_cs0 i/o gpio/ atapi chip select/command block a pj6 / atapi_cs1 i/o gpio/ atapi chip select a pj7 / atapi_dmack i/o gpio/ atapi dma acknowledge a pj8 / atapi_dmarq i/o gpio/ atapi dma request a pj9 / atapi_intrq i/o gpio/ interrupt request from the device a pj10 / atapi_iordy i/o gpio/ atapi ready handshake a pj11 / br 8 i/o gpio/ bus request a pj12 / bg 6 i/o gpio/ bus grant a pj13 / bgh 6 i/o gpio/ bus grant hang a table 11. pin descriptions (continued) pin name i/o 1 function (first/second/third/fourth) driver type 2
rev. d | page 30 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 ddr memory interface da0C12 o ddr address bus d dba0C1 o ddr bank active strobe d dq0C15 i/o ddr data bus d dqs0C1 i/o ddr data strobe d dqm0C1 o ddr data mask for reads and writes d dclk0C1 o ddr output clock d dclk0C1 o ddr complementary output clock d dcs0C1 oddr chip selects d dclke 9 o ddr clock enable (requires a pull- down if hibernate with ddr self- refresh is used.) d dras o ddr row address strobe d dcas o ddr column address strobe d dwe oddr write enable d ddr_vref i ddr voltage reference ddr_vssr i ddr voltage reference shield (must be connected to gnd.) asynchronous memory interface a1-3 o address bus for async and atapi addresses a d0-15/nd_d0-15/atapi_d0-15 i/o data bus for async, nand and atapi accesses a ams0C3 o bank selects (pull high with a resistor when used as chip select. require pull-ups if hibernate is used.) a abe0 / nd_cle o byte enables:data masks for asynchronous access/ nand command latch enable a abe1 / nd_ale o byte enables:data masks for asynchronous access/ nand address latch enable a aoe / nr_adv o output enable/ nor address data valid a are oread enable/ nor output enable a awe owrite enable a atapi controller pins atapi_pdiag i determines if an 80-pin cable is connected to the host. (pull high or low when unused.) high speed usb otg pins usb_dp i/o usb d+ pin (pull low when unused.) usb_dm i/o usb d- pin (pull low when unused.) usb_xi c clock xtal input (pull high or low when unused.) usb_xo c clock xtal output (leave unconnected when unused.) usb_id 10 i usb otg id pin (pull high when unused.) table 11. pin descriptions (continued) pin name i/o 1 function (first/second/third/fourth) driver type 2
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 31 of 100 | may 2011 usb_vbus 11 i/o usb vbus pin (pull high or low when unused.) usb_vref a usb voltage reference (connect to gnd through a 0.1 f capacitor or leave unconnected when not used.) usb_rset a usb resistance set (conne ct to gnd through an unpopulated resistor pad.) mxvr (most) interface mfs o mxvr frame sync (leave unconnected when unused.) c mlf_p a mxvr loop filter plus (leave unconnected when unused.) mlf_m a mxvr loop filter minus (leave unconnected when unused.) mxi c mxvr crystal input (pull high or low when unused.) mxo c mxvr crystal output (pull high or low when unused.) mode control pins bmode0C3 i boot mode strap 0C3 jtag port pins tdi i jtag serial data in tdo o jtag serial data out c trst i jtag reset (pull low when unused.) tms i jtag mode select tck i jtag clock emu o emulation output c voltage regulator vr out 0, vr out 1 o external fet/bjt drivers (always connect together to reduce signal impedance.) real time clock rtxo c rtc crystal output (leave unconnected when unused. does not three- state during hibernate.) rtxi c rtc crystal input (pull high or low when unused.) clock (pll) pins clkin c clock/crystal input clkout o clock output b xtal c crystal output (if clkbuf is enabled, does not three-state during hibernate.) clkbuf o buffered oscillator output (if enabled, does not three-state during hibernate.) c ext_wake o external wakeup from hibernat e output (does not three-state during hibernate.) a reset i reset nmi i non-maskable interrupt (pull high when unused.) table 11. pin descriptions (continued) pin name i/o 1 function (first/second/third/fourth) driver type 2
rev. d | page 32 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 supplies v ddint p internal power supply v ddext 12 p external power supply v ddddr 12 p external ddr power supply v ddusb 12 p external usb power supply v ddrtc 12 p rtc clock supply v ddvr 13 p internal voltage regulator power supply (connect to v ddext when unused.) gnd g ground v ddmp 12 p mxvr pll power supply. (must be driven to same level as v ddint . connect to v ddint when unused or when mxvr is not present.) gnd mp 12 g mxvr pll ground (connect to gnd when unused or when mxvr is not present.) 1 i = input, o = output, p =power, g = ground, c = crystal, a = analog. 2 refer to table 62 on page 86 through table 71 on page 87 for driver types. 3 to use the spi memory boot, spi0sck should have a pulldown, spi0miso should have a pullup, and spi0sel1 is used as the cs with a pullup. 4 hwait/hwaita should be pulled high or low to configure polarity. see booting modes on page 18 . 5 gpw functionality is available when mxvr is not present or unused. 6 this pin should not be used as gpio if booting in mode 1. 7 this pin should always be enabled as nd_ce in software and pulled high with a resistor when using nand flash. 8 this pin should always be enabled as br in software and pulled high to enable asynchronous access. 9 this pin must be pulled low through a 10kohm resistor if self-refresh mode is desired during hibernate state or deep-sleep mode . 10 if the usb is used in device mode only, the usb_id pin should be either pulled high or left unconnected. 11 this pin is an output only during initialization of usb otg session request pulses in peripheral mode. therefore, host mode or otg type a mode requires that an external voltage source of 5 v, at 8 ma or more per the otg specification, be applied to this pin. other otg modes require that this exter nal voltage be disabled. 12 to ensure proper operation, the power pins should be driven to their specified level even if the associated peripheral is not u sed in the application. 13 this pin must always be connected. if the internal voltage regulator is not being used, this pin may be connected to v ddext . otherwise it should be powered according to the vddvr specification. for automotive grade models, the internal voltage regulator must not be used and this pin must be tied to v ddext . table 11. pin descriptions (continued) pin name i/o 1 function (first/second/third/fourth) driver type 2
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 33 of 100 | may 2011 specifications operating conditions parameter conditions min nominal max unit v ddint 1, 2 1 see table 12 on page 34 for frequency/volta ge specif ications. 2 v ddint maximum is 1.10 v during one-time-progra mmable (otp) memory programming operations. internal supply voltage nonautomotive grade models 0.9 1.43 v internal supply voltage automotive and extended temp grade models 1.0 1.38 v internal supply voltage mobile ddr sdram models 1.14 1.31 v v ddext 3 3 v ddext minimum is 3.0 v and maximum is 3.6 v during otp memory programming operations. external supply voltage nonautomotive 3.3 v i/o 2.7 3.3 3.6 v external supply voltage nonautomotive 2.5 v i/o 2.25 2.5 2.75 v external supply voltage automotive and extended temp grade models 2.7 3.3 3.6 v v ddusb usb external supply voltage 3.0 3.3 3.6 v v ddmp mxvr pll supply voltage nonautomotive grade models 0.9 1.43 v mxvr pll supply voltage automotive and extended temp grade models 1.0 1.38 v v ddrtc real time clock supply voltage nonautomotive grade models 2.25 3.6 v real time clock supply voltage automotive and extended temp grade models 2.7 3.3 3.6 v v ddddr ddr memory supply voltage ddr sdram models 2.5 2.6 2.7 v ddr memory supply voltage mobile ddr sdram models 1.8 1.875 1.95 v v ddvr 4 4 use of the internal voltage regulator is no t supported on 600 mhz speed grade models or on automotive grade models. an external voltage regulator must be used. internal voltage regulator supply voltage 2.7 3.3 3.6 v v ih high level input voltage 5, 6 5 bidirectional pins (d15C0, pa15C0, pb14C0, pc15C0, pd15C0, pe15C0 , pf15C0, pg15C0, ph13C0, pi15C0, pj14C0) and input pins (atap i_pdiag , usb_id, tck, tdi, tms, trst , clkin, reset , nmi , and bmode3C0) of the adsp-bf 54x blackfin processors ar e 3.3 v-tolerant (always ac cept up to 3.6 v maximum v ih ). voltage compliance (on outputs, v oh ) is limited by the v ddext supply voltage. the regulator can generate v ddint at levels of 0.90 v to 1.30 v with -5% to +5% tolerance. 6 parameter value applies to all input and bidirectional pins except pb1-0, pe15-14, pg15C11, ph7-6, dq0-15, and dqs0-1. v ddext =maximum 2.0 3.6 v v ihddr high level input voltage 7 7 parameter value applies to pins dq0C15 and dqs0C1. ddr sdram models v ddr_vref + 0.15 v ddddr + 0.3 v high level input voltage 7 mobile ddr sdram models v ddr_vref + 0.125 v ddddr + 0.3 v v ih5v 12 high level input voltage 8 8 pb1-0, pe15-14, pg15-11, and ph7-6 are 5.0 v-to lerant (always accept up to 5.5 v maximum v ih when power is applied to v ddext pins). voltage compliance (on output v oh ) is limited by v ddext supply voltage. v ddext =maximum 2.0 5.5 v v ihtwi high level input voltage 9, 13 v ddext =maximum 0.7 v ddext 5.5 v v ihusb high level input voltage 10 5.25 v v il low level input voltage 5, 11 v ddext = minimum C0.3 0.6 v v il5v low level input voltage 12 3.3 v i/o, v ddext = minimum C0.3 0.8 v low level input voltage 12 2.5 v i/o, v ddext = minimum C0.3 0.6 v v ilddr low level input voltage 7 ddr sdram models C0.3 v ddr_vref C 0.15 v low level input voltage 7 mobile ddr sdram models C0.3 v ddr_vref C 0.125 v v iltwi low level input voltage 9, 13 C0.3 0.3 v ddext v v ddr_vref ddr_vref pin input voltage 0.49 v ddddr 0.50 x v ddddr 0.51 v ddddr v t j 14 junction temperature (400/533 mhz) 400-ball csp_bga @t ambient = C40 o c to +85 o c C40 +105 o c junction temperature (600 mhz) 400-ball csp_bga @t ambient = 0 o c to +70 o c 0+90 o c junction temperature (400 mhz) 400-ball csp_bga @t ambient = C40 o c to +105 o c C40 +125 o c
rev. d | page 34 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 table 12 and table 15 describe the voltage/frequency require- ments for the adsp-bf54x blackfin processors clocks. take care in selecting msel, ssel, an d csel ratios so as not to exceed the maximum core clock and system clock. table 14 describes the phase-locked loop operating conditions. 9 sda and scl are 5.0v tolerant (always accept up to 5.5v maximum v ih ). voltage compliance on outputs (v oh ) is limited by the vddext supply voltage. 10 parameter value applies to usb_dp, usb_dm, and usb_vbus pins. see absolute maximum ratings on page 39 . 11 parameter value applies to all input and bidirectional pins, except pb1-0, pe15-14, pg15C11, and ph7-6. 12 parameter value applies to pins pg15C11 and ph7-6. 13 parameter value applies to pins pb 1-0 and pe15-14. consult the i 2 c specification version 2.1 for the pr oper resistor value and other open drain pin electrical parameters. 14 t j must be in the range: 0c < t j < 55c during otp memo ry programming operations. table 12. core clock (cclk) requirements?533 mhz and 600 mhz speed grade 1 parameter min v ddint internal regulator setting 2 max cclk frequency unit f cclk core clock frequency 1.30 v n/a 2 600 mhz 1.188 v 1.25 v 533 mhz 1.14 v 1.20 v 500 mhz 1.045 v 1.10 v 444 mhz 0.95 v 1.00 v 400 mhz 0.90 v 0.95 v 333 mhz 1 see the ordering guide on page 99 . 2 use of an internal voltage regulator is not supported on automotive grade and 600 mhz speed grade models. internal regulator se tting should be used as recommended nominal v ddint for external regulator. table 13. core clock (cclk) requirements?400 mhz speed grade 1 parameter min v ddint internal regulator setting 2 max cclk frequency unit f cclk core clock frequency 1.14 v 1.20 v 400 mhz 1.045 v 1.10 v 364 mhz 0.95 v 1.00 v 333 mhz 0.90 v 0.95 v 300 mhz 1 see ordering guide on page 99 . 2 use of an internal voltage regulator is not supported on automotive grade models. internal regulator setting should be used as recommended nominal v ddint for external regulator. table 14. phase-locked loop operating conditions parameter min max unit f vco voltage controlled oscillator (vco) frequency 50 maximum f cclk mhz table 15. system clock requirements parameter condition ddr sdram models mobile ddr sdram models unit max min max f sclk v ddint 1.14 v 1 , non-extended temperature grades 133 2 120 3 133 2 mhz f sclk v ddint < 1.14 v 1 , non-extended temperature grades 100 n/a 4 n/a 4 mhz f sclk v ddint 1.0 v 1 , extended temperature grade 100 n/a n/a mhz 1 f sclk must be less than or equal to f cclk . 2 rounded number. actual test specification is sclk period of 7.5 ns. see table 25 on page 42 . 3 rounded number. actual test specification is sclk period of 8.33 ns. 4 v ddint must be greater than or equal to 1.14 v for mobile ddr sdram models. see operating conditions on page 33 .
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 35 of 100 | may 2011 electrical characteristics nonautomotive 400 mhz 1 all other devices 2 parameter test conditions min typ max min typ max unit v oh high level output voltage for 3.3 v i/o 3 v ddext = 2.7 v, i oh = C0.5 ma 2.4 2.4 v high level output voltage for 2.5 v i/o 3 v ddext = 2.25 v, i oh = C0.5 ma 2.0 2.0 v v ohddr high level output voltage for ddr sdram 4 v ddddr = 2.5 v, i oh = C8.1 ma 1.74 1.74 v high level output voltage for mobile ddr sdram 4 v ddddr = 1.8 v, i oh = C0.1 ma 1.62 1.62 v v ol low level output voltage for 3.3 v i/o 3 v ddext = 2.7 v, i ol = 2.0 ma 0.4 0.4 v low level output voltage for 2.5 v i/o 3 v ddext = 2.25 v, i ol = 2.0 ma 0.4 0.4 v v olddr low level output voltage for ddr sdram 4 v ddddr = 2.5 v, i ol = 8.1 ma 0.56 0.56 v low level output voltage for mobile ddr sdram 4 v ddddr = 1.8 v, i ol = 0.1 ma 0.18 0.18 v i ih high level input current 5 v ddext =3.6 v, v in = v in max 10.0 10.0 a i ihp high level input current 6 v ddext =3.6 v, v in =v in max 50.0 50.0 a i ihddr_vref high level input current for ddr sdram 7 v ddddr =2.7 v, v in = 0.51 v ddddr 30.0 30.0 a high level input current for mobile ddr sdram 7 v ddddr =1.95 v, v in = 0.51 v ddddr 30.0 30.0 a i il 8 low level input current v ddext =3.6 v, v in = 0 v 10.0 10.0 a i ozh 9 three-state leakage current 10 v ddext =3.6 v, v in = v in max 10.0 10.0 a i ozl 11 three-state leakage current 10 v ddext =3.6 v, v in = 0 v 10.0 10.0 a c in input capacitance 12 f in = 1 mhz, t ambient = 25c, v in = 2.5 v 4 12 8 12 4 12 8 12 pf i dddeepsleep 13 v ddint current in deep sleep mode v ddint = 1.0 v, f cclk = 0 mhz, f sclk = 0 mhz, t j = 25c, asf = 0.00 22 37 ma i ddsleep v ddint current in sleep mode v ddint = 1.0 v, f sclk = 25 mhz, t j =25c 35 50 ma i dd-idle v ddint current in idle v ddint = 1.0 v, f cclk = 50 mhz, t j = 25c, asf = 0.47 44 59 ma
rev. d | page 36 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 i dd-typ v ddint current v ddint = 1.10 v, f cclk = 300 mhz, f sclk = 25 mhz, t j = 25c, asf = 1.00 145 178 ma i dd-typ v ddint current v ddint = 1.20 v, f cclk = 400 mhz, f sclk = 25 mhz, t j = 25c, asf = 1.00 199 239 ma i dd-typ v ddint current v ddint = 1.25 v, f cclk = 533 mhz, f sclk = 25 mhz, t j = 25c, asf = 1.00 301 ma i dd-typ v ddint current v ddint = 1.35 v, f cclk = 600 mhz, f sclk = 25 mhz, t j = 25c, asf = 1.00 360 ma i ddhibernate 13, 14 hibernate state current v ddext = v ddvr = v ddusb = 3.30 v, v ddddr = 2.5 v, t j = 25c, clkin= 0 mhz with voltage regulator off (v ddint = 0 v) 60 60 a i ddrtc v ddrtc current v ddrtc = 3.3 v, t j = 25c 20 20 a i ddusb-fs v ddusb current in full/low speed mode v ddusb = 3.3 v, t j = 25c, full speed usb transmit 9 9 ma i ddusb-hs v ddusb current in high speed mode v ddusb = 3.3 v, t j =25c, high speed usb transmit 25 25 ma i dddeepsleep 13, 15 v ddint current in deep sleep mode f cclk = 0 mhz, f sclk = 0 mhz table 16 table 17 ma i ddsleep 13, 15 v ddinit current in sleep mode f cclk = 0 mhz, f sclk > 0 mhz i dddeepsleep + (0.77 v ddint f sclk ) 16 i dddeepsleep + (0.77 v ddint f sclk ) 16 ma 16 i ddint 15, 17 v ddint current f cclk > 0 mhz, f sclk > 0 mhz i ddsleep + ( table 19 asf) i ddsleep + ( table 19 asf) ma 1 applies to all nonautomotive 400 mhz speed grade models and all extended temperature grade models. see ordering guide . 2 applies to all 533 mhz and 600 mhz speed grade models and automotive 400 mhz speed grade models. see ordering guide . 3 applies to output and bidirectional pins, except usb_vbus and the pins listed in table note 4. 4 applies to pins da0?12, dba0?1, dq0?15, dqs0?1, dqm0?1, dclk1?2, dclk1?2 , dcs0?1 , dclke, dras , dcas , and dwe . 5 applies to all input pins except jtag inputs. 6 applies to jtag input pins (tck, tdi, tms, trst ). 7 applies to ddr_vref pin. 8 absolute value. 9 for ddr pins (dq0-15, dqs0-1), test conditions are v ddddr = maximum, v in = v ddddr maximum. 10 applies to three-statable pins. 11 for ddr pins (dq0-15, dqs0-1), test conditions are v ddddr = maximum, v in = 0v. 12 guaranteed, but not tested nonautomotive 400 mhz 1 all other devices 2 parameter test conditions min typ max min typ max unit
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 37 of 100 | may 2011 total power dissipation has two components: ? static, includin g leakage current ? dynamic, due to transistor switching characteristics many operating conditions can also affect po wer dissipation, including temperature, voltage, operating frequency, and pro- cessor activity. electrical characteristics on page 35 shows the current dissipation for internal circuitry (v ddint ). i dddeepsleep specifies static power dissipati on as a function of voltage (v ddint ) and temperature (see table 16 and table 17 ), and i ddint specifies the total power specification for the listed test conditions, including the dynamic component as a function of voltage (v ddint ) and frequency ( table 19 ). there are two parts to the dynami c component. the first part is due to transistor switching in the core clock (cclk) domain. this part is subject to an activi ty scaling factor (asf) which rep- resents application code runnin g on the processor core and l1/l2 memories ( table 18 ). the asf is combined with the cclk frequency and v ddint dependent data in table 19 to cal- culate this part. the second part is due to transistor switching in the system clock (sclk) domain, which is included in the i ddint specification equation. 13 see the adsp-bf54x blackfin processor hardware reference manual for definition of sleep, deep sleep, and hibernate operating modes. 14 includes current on v ddext , v ddusb , v ddvr , and v ddddr supplies. clock inputs are tied high or low. 15 guaranteed maximum specifications. 16 unit for v ddint is v (volts). unit for f sclk is mhz. example: 1.2 v, 133 mhz would be 0.77 1.2 133 = 122.9 ma added to i dddeepsleep . 17 see table 18 for the list of i ddint power vectors covered. table 16. static current?low power process (ma) 1 voltage (v ddint ) 2 t j (c) 2 0.90 v 0.95 v 1.00 v 1.05 v 1.10 v 1.15 v 1.20 v 1.25 v 1.30 v 1.35 v 1.38 v 1.40 v 1.43 v -40 11.9 13.5 15.5 17.7 20.3 23.3 26.8 30.6 35.0 39.9 43.2 45.5 49.5 0 20.1 22.3 24.7 27.8 31.1 34.9 39.3 44.2 49.6 55.7 59.8 62.5 67.2 25 31.2 34.2 37.5 41.3 45.6 50.3 55.7 61.7 68.2 75.4 80.3 83.6 88.6 45 47.0 51.0 55.5 60.6 66.0 72.0 78.8 86.1 94.2 102.9 108.9 112.8 118.2 55 58.6 63.1 68.3 74.1 80.3 87.1 94.9 103.0 112.0 122.0 128.4 132.8 140.0 70 80.7 86.6 93.0 100.2 108.1 116.7 125.9 136.0 146.8 158.7 166.4 171.6 179.5 85 107.0 114.3 122.5 131.5 141.2 151.7 163.1 175.3 188.5 202.7 211.8 218.0 226.7 100 153.9 163.0 173.3 184.8 197.0 210.0 224.1 239.0 255.1 272.4 283.4 290.8 300.6 105 171.7 181.5 192.7 205.1 218.3 232.4 247.5 263.6 280.9 299.3 308.7 314.9 325.7 115 210.1 221.4 234.2 248.6 263.7 279.9 297.3 311.0 331.1 352.5 366.3 n/a n/a 125 257.9 270.9 285.9 302.5 314.6 334.0 354.3 375.7 399.2 423.8 439.6 n/a n/a 1 values are guaranteed maximum i dddeepsleep for 400 mhz speed-grade devices. 2 valid temperature and voltage ranges are model-specific. see operating conditions on page 33 . table 17. static current?automotive 400 mhz and all 533 mhz/600 mhz speed grade devices (ma) 1 t j (c) 2 voltage (v ddint ) 2 0.90 v 0.95 v 1.00 v 1.05 v 1.10 v 1.15 v 1.20 v 1.25 v 1.30 v 1.35 v 1.38 v 1.40 v 1.43 v -40 19.7 22.1 24.8 27.9 31.4 35.4 39.9 45.0 50.6 57.0 61.2 64.0 70.4 0 45.2 49.9 55.2 61.3 67.9 75.3 83.5 92.6 102.6 113.6 121.0 125.8 135.0 25 80.0 87.5 96.2 105.8 116.4 127.9 140.4 154.1 169.2 185.4 196.1 203.3 218.0 45 124.2 134.8 147.1 160.7 175.3 191.2 208.6 227.3 247.6 269.6 284.0 293.6 312.0 55 154.6 167.2 181.7 197.7 214.9 233.8 254.2 276.1 299.7 325.9 343.1 354.6 374.0 70 209.8 225.6 243.9 264.1 285.8 309.4 334.8 363.5 394.3 427.7 449.4 463.9 489.0 85 281.8 301.3 323.5 350.2 378.5 408.9 442.1 477.9 516.5 557.5 584.2 602.0 629.0 100 366.5 390.5 419.4 452.1 486.9 524.4 564.8 608.2 654.8 704.7 737.0 758.5 793.0 105 403.8 428.3 459.5 494.3 531.7 571.9 614.9 661.5 711.1 763.9 798.5 821.6 864.0 1 values are guaranteed maximum i dddeepsleep for automotive 400 mhz and all 533 mhz and 600 mhz speed grade devices. 2 valid temperature and voltage ranges are model-specific. see operating conditions on page 33 .
rev. d | page 38 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 table 18. activity scaling factors 1 i ddint power vector activity scaling factor (asf) i dd-peak 1.29 i dd-high 1.24 i dd-typ 1.00 i dd-app 0.87 i dd-nop 0.74 i dd-idle 0.47 1 see estimating power for adsp-bf534/bf536/bf537 blackfin processors (ee-297) . the power vector information also applies to the adsp- bf542/adsp-bf544/adsp-bf54 7/adsp-bf548/adsp-bf549 processors. table 19. dynamic current in cclk domain (ma, with asf = 1.0) 1 f cclk (mhz) 2 voltage (v ddint ) 2 0.90 v0.95 v1.00 v1.05 v1.10 v1.15 v1.20 v1.25 v1.30 v1.35 v1.38 v1.40 v1.43 v 100 29.7 31.6 33.9 35.7 37.9 40.5 42.9 45.5 48.2 50.8 52.0 53.5 54.6 200 55.3 58.9 62.5 66.0 70.0 74.0 78.3 82.5 86.7 91.3 93.3 95.6 97.6 300 80.8 85.8 91.0 96.0 101.3 107.0 112.8 118.7 124.6 130.9 133.8 137.0 140.0 400 n/a 112.2 119.4 125.5 132.4 139.6 146.9 154.6 162.3 170.0 173.8 177.8 181.6 500 n/a n/a n/a n/a n/a 171.9 180.6 189.9 199.1 205.7 210.3 213.0 217.6 533 n/a n/a n/a n/a n/a n/a 191.9 201.6 211.5 218.0 222.8 225.7 230.5 600 n/a n/a n/a n/a n/a n/a n/a n/a 233.1 241.4 246.7 252.7 258.1 1 the values are not guaranteed as stand-alone maximum specifications. they must be combined with static current per the equation s of electrical characteristics on page 35 . 2 valid frequency and voltage ranges are model-specific. see operating conditions on page 33 .
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 39 of 100 | may 2011 absolute maximum ratings stresses greater than those listed in table 20 may cause perma- nent damage to the device. these are stress ratings only. functional operation of the devi ce at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reli- ability. table 21 details the maximum duty cycle for input transient voltage. the absolute maximum ratings table specifies the maximum total source/sink (i oh /i ol ) current for a group of pins. perma- nent damage can occur if this value is exceeded. to understand this specification, if pins pa 4, pa3, pa2, pa1 and pa0 from group 1 in the total current pin groups table were sourcing or sinking 2 ma each, the total current for those pins would be 10 ma. this would allow up to 70 ma total that could be sourced or sunk by the remain ing pins in the group without damaging the device. for a list of all groups and their pins, see the total current pin groups table. note that the v ol and v oh specifications have separate per-pin maximum current require- ments, see the electrical characteristics table. table 20. absolute maximum ratings internal (core) supply voltage (v ddint ) C0.3 v to +1.43 v external (i/o) supply voltage (v ddext )C0.3 v to +3.8 v input voltage 1, 2, 3 1 applies to all bidirectional and input only pins except pb1-0, pe15-14, pg15?11, and ph7-6, where the absolute maximum input voltage range is ?0.5 v to +5.5 v. 2 pins usb_dp, usb_dm, and usb_vbus are 5 v-tolerant when vddusb is powered according to the operating conditions table. if vddusb supply voltage does not meet the specification in the operating conditions table, these pins could suffer long-term damage when driven to +5 v. if this condition is seen in the application, it can be corrected with additional circuitry to use the external host to power only the v ddusb pins. contact factory for application detail and reliability information. 3 applies only when v ddext is within specifications. when v ddext is outside specifications, the range is v ddext 0.2 v. C0.5 v to +3.6 v output voltage swing C0.5 v to v ddext +0.5 v i oh /i ol current per single pin 4 4 for more information, see description preceding table 22 . 40 ma (max) i oh /i ol current per pin group 4 80 ma (max) storage temperature range C65 o c to +150 o c junction temperature underbias +125 o c table 21. maximum duty cycle for input 1 transient voltage 1 does not apply to clkin. absolute maximum for pins pb1-0, pe15-14, pg15- 11, and ph7-6 is +5.5v. v in max (v) 2 2 only one of the listed options can apply to a particular design. v in min (v) maximum duty cycle 3.63 C0.33 100% 3.80 C0.50 48% 3.90 C0.60 30% 4.00 C0.70 20% 4.10 C0.80 10% 4.20 C0.90 8% 4.30 C1.00 5% table 22. total current pin groups group pins in group 1 pa0, pa1, pa2, pa3, pa4, pa5, pa6, pa7, pa8, pa9, pa10, pa11 2 pa12, pa13, pa14, pa15, pb8, pb9, pb10, pb11, pb12, pb13, pb14 3 pb0, pb1, pb2, pb3, pb4, pb5, pb6, pb7, bmode0, bmode1, bmode2, bmode3 4 tck, tdi, tdo, tms, trst , pd14, emu 5 pd8, pd9, pd10, pd11, pd12, pd13, pd15 6 pd0, pd1, pd2, pd3, pd4, pd5, pd6, pd7 7 pe11, pe12, pe13, pf12, pf13, pf14, pf15, pg3, pg4 8 pf4, pf5, pf6, pf7, pf8, pf9, pf10, pf11 9 pf0, pf1, pf2, pf3, pg0, pg1, pg2 10 pc0, pc1, pc2, pc3, pc4, pc5, pc6, pc7 11 ph5, ph6, ph7 12 a1, a2, a3 13 ph8, ph9, ph10, ph11, ph12, ph13 14 pi0, pi1, pi2, pi3, pi4, pi5, pi6, pi7 15 pi8, pi9, pi10, pi11, pi12, pi13, pi14, pi15 16 ams0 , ams1 , ams2 , ams3 , aoe , clkbuf, nmi 17 clkin, xtal, reset , rtxi, rtxo, are , awe 18 d0, d1, d2, d3, d4, d5, d6, d7 19 d8, d9, d10, d11, d12 20 d13, d14, d15, abe0 , abe1 21 ext_wake, clkout, pj11, pj12, pj13 22 pj0, pj1, pj2, pj3, pj4, pj5, pj6, pj7, atapi_pdiag 23 pj8, pj9, pj10, pe7, pg12, pg13 24 pe0, pe1, pe2, pe4, pe5, pe6, pe8, pe9, pe10, ph3, ph4 25 ph0, ph2, pe14, pe15, pg5, pg6, pg7, pg8, pg9, pg10, pg11 26 pc8, pc9, pc10, pc11, pc12, pc13, pe3, pg14, pg15, ph1
rev. d | page 40 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 esd sensitivity package information the information presented in figure 9 and table 23 provides information related to specific product features. for a complete listing of product offerings, see the ordering guide on page 99 . esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality. figure 9. product information on package table 23. package information brand key description bf54x x = 2, 4, 7, 8 or 9 (m) mobile ddr indicator (optional) t temperature range pp package type z rohs compliant part (optional) cc see ordering guide vvvvvv.x-q assembly lot code n.n silicon revision # rohs compliant designation yyww date code vvvvvv.x-q n.n tppz-cc b adsp-bf54x(m) a # yywwcountry_of_origin
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 41 of 100 | may 2011 timing specifications timing specifications are detailed in this section. clock and reset timing table 24 and figure 10 describe clock input and reset timing. table 25 and figure 11 describe clock out timing. table 24. clock input and reset timing parameter min max unit timing requirement s t ckin clkin period 1, 2, 3, 4 20.0 100.0 ns t ckinl clkin low pulse 2 8.0 ns t ckinh clkin high pulse 2 8.0 ns t bufdlay clkin to clkbuf delay 10 ns t wrst reset asserted pulsewidth low 5 11 t ckin ns t rhwft reset high to first hwait/hwaita transition (boot host wait mode) 6, 7, 8, 9 6100 t ckin + 7900 t sclk ns t rhwft reset high to first hwait/hwaita transition (reset output mode) 7, 10, 11 6100 t ckin 7000 t ckin ns 1 combinations of the clkin frequency and the pll clock multiplier must not exceed the allowed f vco , f cclk , and f sclk settings discussed in table 15 and table 12 on page 34 . 2 applies to pll bypass mode and pll non-bypass mode. 3 clkin frequency and duty cycle must not change on the fly. 4 if the df bit in the pll_ctl register is set, then the maximum t ckin period is 50 ns. 5 applies after power-up sequence is complete. see table 26 and figure 12 for more information about power-up reset timing. 6 maximum value not specified due to variation resulting from boot mode selection and otp memory programming. 7 values specified assume no invalidation preboot settings in otp page pbs00l. invalidating a pbs set will increase the value by 1875 t ckin (typically). 8 applies only to boot modes bmode=1, 2, 4, 6, 7, 10, 11, 14, 15. 9 use default t sclk value unless pll is reprogrammed during preboot. in case of pll reprogramming use the new t sclk value and add pll_lockcnt settle time. 10 when enabled by otp_resetout_hwait bit. if regular hwait is not required in an application, the otp_resetout_hwait bit in the s ame page instructs the hwait or hwaita to simulate reset output functionality. then an external resistor is expected to pull the signal to the reset l evel, as the pin itself is in high performance mode during reset. 11 variances are mainly dominated by pll programming instructions in pbs00l page and boot code differences between silicon revisio ns. the earlier is bypassed in boot mode bmode = 0. maximum value assumes pll programming instructions do not cause the sclk frequency to decrease. figure 10. clock and reset timing clkin t wrst t ckin t ckinl t ckinh t bufdlay t bufdlay reset clkbuf hwait (a) t rhwft
rev. d | page 42 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 in figure 12 , v dd_supplies is v ddint , v ddext , v ddddr , v ddusb , v ddrtc , v ddvr , and v ddmp . table 25. clock out timing parameter min max unit switching characteristics t sclk clkout period 1, 2 7.5 ns t sclkh clkout width high 2.5 ns t sclkl clkout width low 2.5 ns 1 the t sclk value is the inverse of the f sclk specification. reduced supply voltages affect the best-case value of 7.5 ns listed here. 2 the t sclk value does not account for the effects of jitter. figure 11. clkout interface timing table 26. power-up reset timing parameter min max unit timing requirement s t rst_in_pwr reset deasserted after the v ddint , v ddext , v ddddr ,v ddusb ,v ddrtc ,v ddvr ,v ddmp , and clkin pins are stable and within specification 3500 t ckin ns t sclkl t sclkh t sclk clkout figure 12. power -up reset timing reset t rst_in_pwr clkin v dd_supplies
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 43 of 100 | may 2011 asynchronous memory read cycle timing table 27 and table 28 on page 44 and figure 13 and figure 14 on page 44 describe asynchronous memory read cycle opera- tions for synchronous and for asynchronous ardy. table 27. asynchronous memory read cycle timing with synchronous ardy parameter min max unit timing requirements t sdat data15C0 setup before clkout 5.0 ns t hdat data15C0 hold after clkout 0.8 ns t sardy ardy setup before the falling edge of clkout 5.0 ns t hardy ardy hold after the falling edge of clkout 0.0 ns switching characteristics t do output delay after clkout 1 6.0 ns t ho output hold after clkout 1 0.3 ns 1 output pins include ams3?0 , abe1?0 , addr19?1, aoe , and are . figure 13. asynchronous memory read cycle timing with synchronous ardy t sardy t hardy t sardy t hardy setup 2 cycles programmed read access 4 cycles access extended 3 cycles hold 1 cycle t do t ho t do t sdat t hdat clkout amsx abe1C0 addr19C1 aoe are ardy data 15C0 t ho
rev. d | page 44 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 table 28. asynchronous memory read cycle timing with asynchronous ardy parameter min max unit timing requirements t sdat data15C0 setup before clkout 5.0 ns t hdat data15C0 hold after clkout 0.8 ns t danr ardy negated delay from amsx asserted 1 (s + ra C 2) t sclk ns t haa ardy asserted hold after are negated 0.0 ns switching characteristics t do output delay after clkout 2 6.0 ns t ho output hold after clkout 2 0.3 ns 1 s = number of programmed setup cycles, ra = number of programmed read access cycles. 2 output pins include ams3?0 , abe1?0 , addr19?1, aoe , and are . figure 14. asynchronous memory read cycle timing with asynchronous ardy setup 2 cycles programmed read access 4 cycles access extended 3 cycles hold 1 cycle t do t ho t do t danr t sdat t hdat clkout amsx abe1C0 addr19C1 aoe are ardy data 15C0 t ho t haa
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 45 of 100 | may 2011 asynchronous memory write cycle timing table 29 and table 30 on page 46 and figure 15 and figure 16 on page 46 describe asynchronous memory write cycle opera- tions for synchronous and for asynchronous ardy. table 29. asynchronous memory write cycle timing with synchronous ardy parameter min max unit timing requirements t sardy ardy setup before the falling edge of clkout 5.0 ns t hardy ardy hold after the falling edge of clkout 0.0 ns switching characteristics t ddat data15C0 disable after clkout 6.0 ns t endat data15C0 enable after clkout 0.0 ns t do output delay after clkout 1 6.0 ns t ho output hold after clkout 1 0.3 ns 1 output pins include ams3?0 , abe1?0 , addr19?1, and awe . figure 15. asynchronous me mory write cycle timing with synchronous ardy setup 2 cycles programmed write access 2 cycles access extend 1 cycle hold 1 cycle t do t ho clkout amsx abe1C0 addr19C1 awe data 15C0 t do t sardy t ddat t endat t ho t hardy t hardy ardy t sardy
rev. d | page 46 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 table 30. asynchronous memory write cycle timing with asynchronous ardy parameter min max unit timing requirements t danw ardy negated delay from amsx asserted 1 (s + wa C 2) t sclk ns t haa ardy asserted hold after awe negated 0.0 ns switching characteristics t ddat data15C0 disable after clkout 6.0 ns t endat data15C0 enable after clkout 0.0 ns t do output delay after clkout 2 6.0 ns t ho output hold after clkout 2 0.3 ns 1 s = number of programmed setup cycles, wa = number of programmed write access cycles. 2 output pins include ams3?0 , abe1?0 , addr19?1, aoe, and awe . figure 16. asynchronous memory write cycle timing with asynchronous ardy setup 2 cycles programmed write access 2 cycles access extended 2 cycles hold 1 cycle t do t ho clkout amsx abe1C0 addr19C1 awe ardy data 15C0 t do t ddat t endat t ho t danw t haa
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 47 of 100 | may 2011 ddr sdram/mobile ddr sdram clock and control cycle timing table 31 and figure 17 describe ddr sdram/mobile ddr sdram clock and control cycle timing. table 31. ddr sdram/mobile ddr sdram clock and control cycle timing ddr sdram mobile ddr sdram unit parameter min max min max switching characteristics t ck 1 dck0-1 period, non-extended temperature grade models 7.50 7.50 8.33 ns dck0-1 period, extended temperature grade models 10.00 n/a n/a ns t ch dck0-1 high pulse width 0.45 0.55 0.45 0.55 t ck t cl dck0-1 low pulse width 0.45 0.55 0.45 0.55 t ck t as 2, 3 address and control output setup time relative to ck 1.00 1.00 ns t ah 2, 3 address and control output hold time relative to ck 1.00 1.00 ns t opw 2, 3 address and control output pulse width 2.20 2.30 ns 1 the t ck specification does not account for the effects of jitter. 2 address pins include da0-12 and dba0-1. 3 control pins include dcs0-1 , dclke, dras , dcas , and dwe . figure 17. ddr sdram /m obile ddr sdram clock and control cycle timing note: control = dcs0-1 , dclke, dras , dcas , and dwe . address = da0-12 and dba0-1. dck0-1 address control t as t ah t ck t ch t cl t opw
rev. d | page 48 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 ddr sdram/mobile ddr sdram timing table 32 and figure 18 / figure 19 describe ddr sdram/mobile ddr sdram read cycle timing. table 32. ddr sdram/mobile ddr sdram read cycle timing ddr sdram mobile ddr sdram parameter min max min max unit timing requirements t ac access window of dq0-15 to dck0-1 C1.25 +1.25 0.0 6.00 ns t dqsck access window of dqs0-1 to dck0-1 C1.25 +1.25 0.0 6.00 ns t dqsq dqs0-1 to dq0-15 skew, dqs0-1 to last dq0-15 valid 0.90 0.85 ns t qh dq0-15 to dqs0-1 hold, dqs0-1 to first dq0-15 to go invalid t ck /2 C 1.25 1 t ck /2 C 1.75 2 t ck /2 C 1.25 ns t rpre dqs0-1 read preamble 0.9 1.1 0.9 1.1 t ck t rpst dqs0-1 read postamble 0.4 0.6 0.4 0.6 t ck 1 for 7.50 ns t ck < 10 ns. 2 for t ck 10 ns. figure 18. ddr sdram controller read cycle timing figure 19. mobile ddr sdram controller read cycle timing dck0-1 dqs0-1 t dqsck t ac t rpre t dqsq t qh t rpst dq0-15 dn dn+1 dn+2 dn+3 dck0-1 dqs0-1 t dqsck t ac t dqsq dq0-15 dn dn+1 dn+2 dn+3 t rpre t rpst t qh
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 49 of 100 | may 2011 ddr sdram/mobile ddr sdram write cycle timing table 33 and figure 20 describe ddr sdram/mobile ddr sdram write cycle timing. table 33. ddr sdram/mobile ddr sdram write cycle timing ddr sdram mobile ddr sdram parameter min max min max unit switching characteristics t dqss write cmd to first dqs0-1 0.75 1.25 0.75 1.25 t ck t ds dq0-15/dqm0-1 setup to dqs0-1 0.90 0.90 ns t dh dq0-15/dqm0-1 hold to dqs0-1 0.90 0.90 ns t dss dqs0-1 falling to dck0-1 ri sing (dqs0-1 setup) 0.20 0.20 t ck t dsh dqs0-1 falling from dck0-1 rising (dqs0-1 hold) 0.20 0.20 t ck t dqsh dqs0-1 high pulse width 0.35 0.40 0.60 t ck t dqsl dqs0-1 low pulse width 0.35 0.40 0.60 t ck t wpre dqs0-1 write preamble 0.25 0.25 t ck t wpst dqs0-1 write postamble 0.40 0.60 0.40 0.60 t ck t dopw dq0-15 and dqm0-1 output pulse width (for each) 1.75 1.75 ns figure 20. ddr sdram /mobile ddr sdram controller write cycle timing dck0-1 dqs0-1 dq0-15/dqm0-1 t dqss t dsh t dss t dqsl t dqsh t wpst t wpre t ds t dh t dopw control write cmd dn dn+1 dn+2 dn+3 note: control = dcs0-1 , dclke, dras , dcas , and dwe .
rev. d | page 50 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 external port bus request and grant cycle timing table 34 and table 35 on page 51 and figure 21 and figure 22 on page 51 describe external port bus request and grant cycle operations for synchronous and for asynchronous br . table 34. external port bus request and grant cycle timing with synchronous br parameter min max unit timing requirements t bs br asserted to clkout low setup 5.0 ns t bh clkout low to br deasserted hold time 0.0 ns switching characteristics t sd clkout low to amsx , address, and are /awe disable 5.0 ns t se clkout low to amsx , address, and are /awe enable 5.0 ns t dbg clkout low to bg asserted output delay 4.0 ns t ebg clkout low to bg deasserted output hold 4.0 ns t dbh clkout low to bgh asserted output delay 3.6 ns t ebh clkout low to bgh deasserted output hold 3.6 ns figure 21. external port bus request and grant cycle timing with synchronous br amsx clkout bg bgh br addr 19-1 abe1-0 t bh t bs t sd t se t sd t sd t se t se t ebg t dbg t ebh t dbh awe are
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 51 of 100 | may 2011 table 35. external port bus request and grant cycle timing with asynchronous br parameter min max unit timing requirements t wbr br pulsewidth 2 x t sclk ns switching characteristics t sd clkout low to amsx , address, and are /awe disable 5.0 ns t se clkout low to amsx , address, and are /awe enable 5.0 ns t dbg clkout low to bg asserted output delay 4.0 ns t ebg clkout low to bg deasserted output hold 4.0 ns t dbh clkout low to bgh asserted output delay 3.6 ns t ebh clkout low to bgh deasserted output hold 3.6 ns figure 22. external port bus request and gr ant cycle timing with asynchronous br amsx clkout bg bgh br addr 19-1 abe1-0 t sd t se t sd t sd t se t se t ebg t dbg t ebh t dbh awe are t wbr
rev. d | page 52 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 nand flash controller interface timing table 36 and figure 23 on page 53 through figure 27 on page 55 describe nand flash controller interface operations. in the figures, nd_data is nd_d0Cd15. table 36. nand flash controller interface timing parameter min max unit write cycle switching characteristics t cwl nd_ce setup time to awe low 1.0 t sclk C 4 ns t ch nd_ce hold time from awe high 3.0 t sclk C 4 ns t clhwl nd_cle setup time high to awe low 0.0 ns t clh nd_cle hold time from awe high 2.5 t sclk C 4 ns t allwl nd_ale setup time low to awe low 0.0 ns t alh nd_ale hold time from awe high 2.5 t sclk C 4 ns t wp 1 awe low to awe high (wr_dly +1.0) t sclk C 4 ns t whwl awe high to awe low 4.0 t sclk C 4 ns t wc 1 awe low to awe low (wr_dly +5.0) t sclk C 4 ns t dws 1 data setup time for a write access (wr_dly +1.5) t sclk C 4 ns t dwh data hold time for a write access 2.5 t sclk C 4 ns read cycle switching characteristics t crl nd_ce setup time to are low 1.0 t sclk C 4 ns t crh nd_ce hold time from are high 3.0 t sclk C 4 ns t rp 1 are low to are high (rd_dly +1.0) t sclk C 4 ns t rhrl are high to are low 4.0 t sclk C 4 ns t rc 1 are low to are low (rd_dly + 5.0) t sclk C 4 ns timing requirements t drs data setup time for a read transaction 8.0 ns t drh data hold time for a read transaction 0.0 ns write followed by read switching characteristic t whrl awe high to are low 5.0 t sclk C 4 ns 1 wr_dly and rd_dly are defined in the nfc_ctl register.
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 53 of 100 | may 2011 figure 23. nand flash controller in terface timingcommand wri cycle figure 24. nand flash controller interface timingaddress write cycle t clewl t alewl nd_data t ch t cwl t clh t alh t dwh nd_ce nd_cle nd_ale awe t wp t dws nd_data t wp t wp t alh t alh nd_ce nd_cle nd_ale awe t cwl t clewl t alewl t whwl t wc t dws t dwh t dws t dwh t alewl
rev. d | page 54 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 figure 25. nand flash controller inte rface timingdata write operation figure 26. nand flash controller in terface timingdata read operation nd_data nd_ce nd_cle nd_ale awe t cwl t clewl t alewl t wc t dws t dwh t dws t dwh t whwl t wp t wp nd_data t rp nd_cle nd_ce nd_ale are t crl t crh t rp t rhrl t rc t drs t drh t drs t drh
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 55 of 100 | may 2011 figure 27. nand flash controller interface timingwrite followed by read operation nd_data nd_cle t clwl t clewl t clh are awe t dws t dwh t drs t drh t whrl t wp t rp nd_ce
rev. d | page 56 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 synchronous burst ac timing table 37 and figure 28 on page 56 describe synchronous burst ac operations. table 37. synchronous burst ac timing parameter min max unit timing requirements t nds data15-0 setup before nr_clk 4.0 ns t ndh data15-0 hold after nr_clk 2.0 ns t nws wait setup before nr_clk 8.0 ns t nwh wait hold after nr_clk 0.0 ns switching characteristics t ndo amsx , abe1-0 , addr19-1, nr_adv , nr_oe output delay after nr_clk 6.0 ns t nho abe1-0 , addr19-1 output hold after nr_clk C3.0 ns figure 28. synchronous burst ac interface timing t ndo t ndo t ndo t ndo t ndo t nws t nwh t ndo t ndo t nho t ndh t ndh t nds t nds t ndo t nho dn dn+1 dn+2 dn+3 amsx nr_clk abe1-0 addr19-1 data15-0 nr_adv nr_oe wait note: nr_clk dotted line represents a free running version of nr_clk that is not visible on the nr_clk pin.
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 57 of 100 | may 2011 external dma request timing table 38 and figure 29 describe the external dma request tim- ing operations. table 38. external dma request timing parameter min max unit timing parameters t dr dmarx asserted to clkout high setup 6.0 ns t dh clkout high to dmarx deasserted hold time 0.0 ns t dmaract dmarx active pulse width 1.0 t sclk ns t dmarinact dmarx inactive pulse width 1.75 t sclk ns figure 29. external dma request timing clkout t ds dmar0/1 (active low) dmar0/1 (active high) t dmaract t dmarinact t dh
rev. d | page 58 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 enhanced parallel peripheral interface timing table 39 and figure 32 on page 59 , figure 30 on page 58 , figure 33 on page 59 , and figure 31 on page 58 describe enhanced parallel peripheral in terface timing operations. table 39. enhanced parallel peripheral interface timing parameter min max unit timing requirements t pclkw ppix_clk width 6.0 ns t pclk ppix_clk period 13.3 ns timing requirementsgp input and frame capture modes t sfspe external frame sync setup before ppix_clk 0.9 ns t hfspe external frame sync hold after ppix_clk 1.9 ns t sdrpe receive data setup before ppix_clk 1.6 ns t hdrpe receive data hold after ppix_clk 1.5 ns switching characteristicsgp output and frame capture modes t dfspe internal frame sync delay after ppix_clk 10.5 ns t hofspe internal frame sync hold after ppix_clk 2.4 ns t ddtpe transmit data delay after ppix_clk 9.9 ns t hdtpe transmit data hold after ppix_clk 2.4 ns figure 30. eppi gp rx mode with external frame sync timing figure 31. eppi gp tx mode with external frame sync timing t pclk t sfspe data sampled / frame sync sampled data sampled / frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t hdrpe t sdrpe t pclkw t hdtpe t sfspe data driven / frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t ddtpe t pclk t pclkw
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 59 of 100 | may 2011 figure 32. eppi gp rx mode with internal frame sync timing figure 33. eppi gp tx mode wi th internal frame sync timing t hdrpe t sdrpe t hofspe frame sync driven data sampled ppi_data ppi_clk ppi_fs1/2 t dfspe t pclk t pclkw t hofspe frame sync driven data driven ppi_data ppi_clk ppi_fs1/2 t dfspe t ddtpe t hdtpe t pclk t pclkw data driven
rev. d | page 60 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 serial ports timing table 40 through table 43 on page 62 and figure 34 on page 61 through figure 37 on page 62 describe serial port operations. table 40. serial ports?external clock parameter min max unit timing requirements t sfse tfsx/rfsx setup before tsclkx/rsclk x (externally generated tfsx/rfsx) 1 3.0 ns t hfse tfsx/rfsx hold after tsclkx/rsclk x (externally generated tfsx/rfsx) 1 3.0 ns t sdre receive data setup before rsclkx 1 3.0 ns t hdre receive data hold after rsclkx 1 3.0 ns t sclkew tsclkx/rsclkx width 4.5 ns t sclke tsclkx/rsclkx period 15.0 ns t rclke rsclkx period 2 11.1 ns t sudte start-up delay from sport enable to first external tfsx 4 t sclke ns t sudre start-up delay from sport enable to first external rfsx 4 t rclke ns switching characteristics t dfse tfsx/rfsx delay after tsclkx/rsclk x (internally generated tfsx/rfsx) 3 10.0 ns t hofse tfsx/rfsx hold after tsclkx/rsclk x (internally generated tfsx/rfsx) 3 0.0 ns t ddte transmit data delay after tsclkx 3 10.0 ns t hdte transmit data hold after tsclkx 3 0.0 ns 1 referenced to sample edge. 2 for serial port receive with external clock and external frame sync only. 3 referenced to drive edge. table 41. serial ports?internal clock parameter min max unit timing requirements t sfsi tfsx/rfsx setup before tsclkx/rsclk x (externally generated tfsx/rfsx) 1 10.0 ns t hfsi tfsx/rfsx hold after tsclkx/rsclk x (externally generated tfsx/rfsx) 1 C1.5 ns t sdri receive data setup before rsclkx 1 10.0 ns t hdri receive data hold after rsclkx 1 C1.5 ns switching characteristics t dfsi tfsx/rfsx delay after tsclkx/rsclk x (internally generated tfsx/rfsx) 2 3.0 ns t hofsi tfsx/rfsx hold after tsclkx/rsclk x (internally generated tfsx/rfsx) 2 C1.0 ns t ddti transmit data delay after tsclkx 2 3.0 ns t hdti transmit data hold after tsclkx 2 C2.0 ns t sclkiw tsclkx/rsclkx width 4.5 ns 1 referenced to sample edge. 2 referenced to drive edge.
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 61 of 100 | may 2011 figure 34. serial port start-up with external clock and frame sync figure 35. serial ports tsclkx (input) tfsx (input) rfsx (input) rsclkx (input) t sudte t sudre first tsclkx/rsclkx edge after sport enabled t sdri rsclkx drx drive edge t hdri t sfsi t hfsi t dfsi t h ofsi t sclkiw data receiveinternal clock t sdre data receiveexternal clock rsclkx drx t hdre t sfse t hfse t dfse t sclkew t hofse t ddti t hdti tsclkx tfsx (input) dtx t sfsi t hfsi t sclkiw t dfsi t hofsi data transmitinternal clock t ddte t hdte tsclkx dtx t sfse t dfse t sclkew t hofse data transmitexternal clock sample edge drive edge sample edge drive edge sample edge drive edge sample edge t sclke t sclke t hfse tfsx (output) tfsx (input) tfsx (output) rfsx (input) rfsx (output) rfsx (input) rfsx (output)
rev. d | page 62 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 table 42. serial ports?enable and three-state parameter min max unit switching characteristics t dtene data enable delay from external tsclkx 1 0ns t ddtte data disable delay from external tsclkx 1, 2 10.0 ns t dteni data enable delay from internal tsclkx 1 C2.0 ns t ddtti data disable delay from internal tsclkx 1, 2 3.0 ns 1 referenced to drive edge. 2 applicable to multichannel mode only. figure 36. serial portsenable and three-state table 43. serial ports?external late frame sync parameter min max unit switching characteristics t ddtlfse data delay from late external tfsx or external rfsx in multi-channel mode with mfd = 01 1, 2 10.0 ns t dtenlfse data enable from external rfsx in multi-channel mode with mfd = 0 1, 2 0ns 1 in multichannel mode, tfsx enable and tfsx valid follow t dtenlfs and t ddtlfse . 2 if external rfs/tfs setup to rsclk/tsclk > t sclke /2, then t ddte/i and t dtene/i apply; otherwise t ddtlfse and t dtenlfs apply. figure 37. serial portsexternal late frame sync tsclkx dtx drive edge t ddtte/i t dtene/i drive edge rsclkx rfsx dtx drive edge drive edge sample edge external rfsx in multi-channel mode 1st bit t dtenlfse t ddtlfse tsclkx tfsx dtx drive edge drive edge sample edge late external tfsx 1st bit t ddtlfse
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 63 of 100 | may 2011 serial peripheral interface (spi) portmaster timing table 44 and figure 38 describe spi port master operations. table 44. serial peripheral interface (spi) port?master timing parameter min max unit timing requirements t sspidm data input valid to spixsck edge (data input setup) 9.0 ns t hspidm spixsck sampling edge to data input invalid C1.5 ns switching characteristics t sdscim spixsely low to first spixsck edge 2t sclk C1.5 ns t spichm spixsck high period 2t sclk C1.5 ns t spiclm spixsck low period 2t sclk C1.5 ns t spiclk spixsck period 4t sclk C1.5 ns t hdsm last spixsck edge to spixsely high 2t sclk C1.5 ns t spitdm sequential transfer delay 2t sclk C1.5 ns t ddspidm spixsck edge to data out valid (data out delay) 6 ns t hdspidm spixsck edge to data out invalid (data out hold) C1.0 ns figure 38. serial peripheral interface (spi) portmaster timing t sdscim t spiclk t hdsm t spitdm t spiclm t spichm t hdspidm t hspidm t sspidm spixsely (output) spixsck (output) spixmosi (output) spixmiso (input) spixmosi (output) spixmiso (input) cpha = 1 cpha = 0 t ddspidm t hspidm t sspidm t hdspidm t ddspidm
rev. d | page 64 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 serial peripheral interface (spi) portslave timing table 45 and figure 39 describe spi port slave operations. table 45. serial peripheral interface (spi) port?slave timing parameter min max unit timing requirements t spichs spixsck high period 2t sclk C1.5 ns t spicls spixsck low period 2t sclk C1.5 ns t spiclk spixsck period 4t sclk ns t hds last spixsck edge to spixss not asserted 2t sclk C1.5 ns t spitds sequential transfer delay 2t sclk C1.5 ns t sdsci spixss assertion to first spixsck edge 2t sclk C1.5 ns t sspid data input valid to spixsck edge (data input setup) 1.6 ns t hspid spixsck sampling edge to data input invalid 1.6 ns switching characteristics t dsoe spixss assertion to data out active 0 8 ns t dsdhi spixss deassertion to data high impedance 0 8 ns t ddspid spixsck edge to data out valid (data out delay) 10 ns t hdspid spixsck edge to data out invalid (data out hold) 0 ns figure 39. serial peripheral interface (spi) portslave timing t spiclk t hds t spitds t sdsci t spicls t spichs t dsoe t ddspid t ddspid t dsdhi t hdspid t sspid t dsdhi t hdspid t dsoe t hspid t sspid t ddspid spixss (input) spixsck (input) spixmiso (output) spixmosi (input) spixmiso (output) spixmosi (input) cpha = 1 cpha = 0 t hspid
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 65 of 100 | may 2011 universal asynchronous receiver-transmitter (uart) portsreceive and transmit timing the uart ports have a maximum baud rate of sclk/16. there is some latency between the generation of internal uart inter- rupts and the external data op erations. these latencies are negligible at the data transmission rates for the uart. for more information, see the adsp-bf54x blackfin processor hardware reference . general-purpose port timing table 46 and figure 40 describe general-purpose port operations. table 46. general-purpose port timing parameter min max unit timing requirement t wfi general-purpose port pin input pulse width t sclk + 1 ns switching characteristics t gpod general-purpose port pin output delay from clkout low C0.3 6 ns figure 40. general-purpose port timing clkout gpio output gpio input t wfi t gpod
rev. d | page 66 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 timer clock timing table 47 and figure 41 describe timer clock timing. table 47. timer clock timing parameter min max unit switching characteristic t todp timer output update delay after ppi_clk high 15 ns figure 41. timer clock timing ppi_clk tmrx output t todp
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 67 of 100 | may 2011 timer cycle timing table 48 and figure 42 describe timer expired operations. the input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input fre- quency of (f sclk /2) mhz. table 48. timer cycle timing parameter min max unit timing characteristics t wl timer pulse width input low 1 t sclk +1 ns t wh timer pulse width input high 1 t sclk +1 ns t tis timer input setup time before clkout low 2 6.5 ns t tih timer input hold time after clkout low 2 C1 ns switching characteristics t hto timer pulse width output 1 t sclk (2 32 C 1) t sclk ns t tod timer output delay after clkout high 6 ns 1 the minimum pulse widths apply for tmrx signals in width capture and external clock modes. 2 either a valid setup and hold time or a valid pulse width is sufficient. there is no need to resynchronize timer flag inputs. figure 42. timer cycle timing clkout tmrx output tmrx input t tis t tih t wh ,t wl t tod t hto
rev. d | page 68 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 up/down counter/rotary encoder timing table 49 and figure 43 describe up/down counter/rotary encoder timing. table 49. up/down counter/rotary encoder timing parameter min max unit timing requirements t wcount cud/cdg/czm input pulse width t sclk + 1 ns t cis cud/cdg/czm input setup time before clkout high 1 7.2 ns t cih cud/cdg/czm input hold time after clkout high 1 0.0 ns 1 either a valid setup and hold time or a valid pulse width is sufficient. there is no need to resynchronize counter inputs. figure 43. up/down counter/rotary encoder timing clkout cud/cdg/czm t cis t cih t wcount
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 69 of 100 | may 2011 sd/sdio controller timing table 50 and figure 44 describe sd/sdio controller timing. table 51 and figure 45 describe sd/sdio controller (high- speed mode) timing. table 50. sd/sdio controller timing parameter min max unit timing requirements t isu sd_dx and sd_cmd input setup time 7.2 ns t ih sd_dx and sd_cmd input hold time 2 ns switching characteristics f pp sd_clk frequency during data transfer mode 1 020 mhz f od sd_clk frequency during identification mode 100 2 400 khz t wl sd_clk low time 15 ns t wh sd_clk high time 15 ns t tlh sd_clk rise time 10 ns t thl sd_clk fall time 10 ns t odly sd_dx and sd_cmd output delay time during data transfer mode C1 14 ns t odly sd_dx and sd_cmd output delay time during identification mode C1 50 ns 1 t pp =1/f pp 2 spec can be 0 khz, meaning to stop the clock. the given minimum frequency range is for cases where a continuous clock is requir ed. figure 44. sd/sdio controller timing sd_clk input output t isu notes: 1 input includes sd_dx and sd_cmd signals. 2 output includes sd_dx and sd_cmd signals. t thl t tlh t wl t wh t pp t ih t odly v oh (min) v ol (max)
rev. d | page 70 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 table 51. sd/sdio controller timing (high speed mode) parameter min max unit timing requirements t isu sd_dx and sd_cmd input setup time 7.2 ns t ih sd_dx and sd_cmd input hold time 2 ns switching characteristics f pp sd_clk frequency during data transfer mode 1 040mhz t wl sd_clk low time 9.5 ns t wh sd_clk high time 9.5 ns t tlh sd_clk rise time 3ns t thl sd_clk fall time 3ns t odly sd_dx and sd_cmd output delay time during data transfer mode 2 ns t oh sd_dx and sd_cmd output hold time 2.5 ns 1 t pp =1/f pp figure 45. sd/sdio controller timing (high speed mode) sd_clk input output t isu notes: 1 input includes sd_dx and sd_cmd signals. 2 output includes sd_dx and sd_cmd signals. t thl t tlh t wl t wh t pp t ih t odly t oh v oh (min) v ol (max)
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 71 of 100 | may 2011 mxvr timing table 52 and table 53 describe the mxvr timing requirements. figure 5 illustrates the most connection. table 52. mxvr timing?mxi center frequency requirements parameter fs = 38 khz fs = 44.1 khz fs = 48 khz unit f mxi_256 mxi center frequency (256 fs) 9.728 11.2896 12.288 mhz f mxi_384 mxi center frequency (384 fs) 14.592 16.9344 18.432 mhz f mxi_512 mxi center frequency (512 fs) 19.456 22.5792 24.576 mhz f mxi_1024 mxi center frequency (1024 fs) 38.912 45.1584 49.152 mhz table 53. mxvr timing? mxi clock requirements parameter min max unit timing requirement s fs mxi mxi clock frequency stability C50 +50 ppm ft mxi mxi frequency tolerance over temperature C300 +300 ppm dc mxi mxi clock duty cycle +40 +60 %
rev. d | page 72 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 hostdp a/c timing-host read cycle table 54 and figure 46 describe the hostdp a/c host read cycle timing requirements. table 54. host read cycl e timing requirements parameter min max units timing requirements t sadrdl host_addr and host_ce setup before host_rd falling edge 4 ns t hadrdh host_addr and host_ce hold after host_rd rising edge 2.5 ns t rdwl host_rd pulse width low (ack mode) t drdyrdl + t rdyprd + t drdhrdy ns t rdwl host_rd pulse width low (int mode) 1.5 t sclk + 8.7 ns t rdwh host_rd pulse width high or time between host_rd rising edge and host_wr falling edge 2 t sclk ns t drdhrdy host_rd rising edge delay after host_ack rising edge (ack mode) 0 ns switching characteristics t sdatrdy host_d15C0 valid prior host_ack rising edge (ack mode) t sclk C 4.0 ns t drdyrdl host_ack falling edge after host_ce (ack mode) 11.25 ns t rdyprd host_ack low pulse-width for read access (ack mode) nm 1 ns t ddarwh host_d15C0 disable after host_rd 8.0 ns t acc host_d15C0 valid after host_rd falling edge (int mode) 1.5 t sclk ns t hdarwh host_d15C0 hold after host_rd rising edge 1.0 ns 1 nm (not measured) ? this parameter is based on t sclk . it is not measured because the number of sclk cycles for which host_ack remains low depends on the host dma fifo status. this is system design dependent. in figure 46 , host_data is host_d0Cd15. figure 46. hostdp a/ chost read cycle host_rd host_ack host_data t sadrdl t hadrdh t drdhrdy t hdarwh t rdyprd t drdyrdl t sdatrdy host_addr host_ce t rdwl t rdwh t acc t ddarwh
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 73 of 100 | may 2011 hostdp a/c timing-host write cycle table 55 and figure 47 describe the hostdp a/c host write cycle timing requirements. table 55. host write cycle timing requirements parameter min max unit timing requirements t sadwrl host_addr/host_ce setup before host_wr falling edge 4 ns t hadwrh host_addr/host_ce hold after host_wr rising edge 2.5 ns t wrwl host_wr pulse width low (ack mode) t drdywrl + t rdyprd + t dwrhrdy ns host_wr pulse width low (int mode) 1.5 t sclk + 8.7 ns t wrwh host_wr pulse width high or time between host_wr rising edge and host_rd falling edge 2 t sclk ns t dwrhrdy host_wr rising edge delay after host_ack rising edge (ack mode) 0 ns t hdatwh host_d15C0 hold after host_wr rising edge 2.5 ns t sdatwh host_d15C0 setup before host_wr rising edge 3.5 ns switching characteristics t drdywrl host_ack falling edge after host_ce asserted (ack mode) 11.25 ns t rdypwr host_ack low pulse-width for write access (ack mode) nm 1 ns 1 nm (not measured)?this parameter is based on t sclk . it is not measured because the number of sclk cycles for which host_ack remains low depends on the host dma fifo status. this is system design dependent. in figure 47 , host_data is host_d0Cd15. figure 47. hostdp a/c- host write cycle host_wr host_ack host_data t sadwrl t hadwrh t dwrhrdy t rdypwr t drdywrl t sdatwh host_addr host_ce t wrwl t wrwh t hdatwh
rev. d | page 74 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 ata/atapi-6 interface timing the following tables and figure s specify atapi timing parame- ters. for detailed parameter descriptions, refer to the atapi specification (ansi incits 361-2002). table 58 to table 61 include atapi timing parameter equations. system designers should use these equations along with the parameters provided in table 56 and table 57 . atapi timing control registers should be programmed such that ansi incits 361-2002 speci- fications are met for the desi red transfer ty pe and mode. table 56. ata/atapi-6 timing parameters parameter min max unit t sk1 difference in output delay after clkout for atapi output pins 1 6ns t od output delay after clkout for outputs 1 12 ns t sud atapi_d0-15 or atapi_d0-15a setup before clkout 6 ns t sui atapi_iordy setup before clkout 6 ns t sudu atapi_d0-15 or atapi_d0-15a setup before atapi_iordy (udma-in only) 2 ns t hdu atapi_d0-15 or atapi_d0-15a hold after atapi_iordy (udma-in only) 2.6 ns 1 atapi output pins include atapi_cs0 , atapi_cs1 , a1-3, atapi_dior , atapi_diow , atapi_dmack , atapi_d0-15, atapi_a0-2a, and atapi_d0-15a. table 57. ata/atapi-6 system timing parameters parameter source t sk2 maximum difference in board propagation delay between any 2 atapi output pins 1 system design t bd maximum board propagation delay. system design t sk3 maximum difference in board propagation delay during a read between atapi_iordy and atapi_d0- 15/atapi_d0-15a. system design t sk4 maximum difference in atapi cable propagation delay between output pin group a and output pin group b 2 atapi cable specification t cdd atapi cable propagation delay for atapi_d0-15 and atapi_d0-15a signals. atapi cable specification t cdc atapi cable propagation delay for atapi_dior , atapi_diow , atapi_iordy , and atapi_dmack signals. atapi cable specification 1 atapi output pins include atapi_cs0 , atapi_cs1 , a1-3, atapi_dior , atapi_diow , atapi_dmack , atapi_d0-15, atapi_a0-2a, and atapi_d0-15a. 2 output pin group a includes atapi_dior , atapi_diow , and atapi_dmack . output pin group b includes atapi_cs0 , atapi_cs1 , a1-3, atapi_d0-15, atapi_a0-2a, and atapi_d0-15a.
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 75 of 100 | may 2011 register and pio table 58 and figure 48 describe the atapi register and the pio data transfer timing. the material in this figure is adapted from atapi-6 (incits 361-2002[r2007] and is used with permis- sion of the american national standards institute (ansi) on behalf of the information technology industry council (itic). copies of atapi- 6 (incits 361-2002 [r2007] can be purchased from ansi. note that in figure 48 atapi_addr pins include a1-3, atapi_cs0 , and atapi_cs1 . alternate atapi port atapi_addr pins include atapi_a0a, atapi_a1a, atapi_a2a, atapi_cs0 , and atapi_cs1 . note that an alternate atapi_d0-15 port bus is atapi_d0-15a table 58. atapi register and pio data transfer timing atapi parameter/description atapi_reg/pio_tim_x timing register setting 1 timing equation t 0 cycle time t2_pio, teoc_pio (t2_pio + teoc_pio) t sclk t 1 atapi_addr valid to atapi_dior /atapi_diow setup t1 t1 t sclk C (t sk1 + t sk2 + t sk4 ) t 2 atapi_dior /atapi_diow pulse width t2_pio t2_pio t sclk t 2i atapi_dior /atapi_diow recovery time teoc_pio teoc_pio t sclk t 3 atapi_diow data setup t2_pio t2_pio t sclk C (t sk1 + t sk2 + t sk4 ) t 4 atapi_diow data hold t4 t4 t sclk C (t sk1 + t sk2 + t sk4 ) t 5 atapi_dior data setup n/a t od + t sud + 2 t bd + t cdd + t cdc t 6 atapi_dior data hold n/a 0 t 9 atapi_dior /atapi_diow to atapi_addr valid hold teoc_pio teoc_pio t sclk C (t sk1 + t sk2 + t sk4 ) t a atapi_iordy setup time t2_pio t2_pio t sclk C (t od + t sui + 2 t cdc + 2 t bd ) 1 atapi timing register setting should be programmed with a value that guarantees parameter compliance with the ata ansi specific ation for the ata device mode of operation. figure 48. reg and pio data transfer timing atapi addr t 0 t 2 t 9 t 3 t 4 t 5 t a t 6 t 2i t 1 atapi_dior/ atapi_diow atapi_d0C15 atapi_iordy atapi_iordy atapi_d0C15 (write) (read)
rev. d | page 76 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 atapi multiword dma transfer timing table 59 and figure 49 through figure 52 describe the atapi multiword dma transfer timing. th e material in these figures is adapted from atapi-6 (incit s 361-2002[r2007] and is used with permission of the american national standards institute (ansi) on behalf of the info rmation technology industry council (itic). copies of atapi-6 (incits 361-2002 [r2007] can be purchased from ansi. table 59. atapi multiword dma transfer timing atapi parameter/description atapi_multi_tim_x timing register setting 1 timing equation t 0 cycle time td, tk (td + tk) t sclk t d atapi_dior /atapi_diow asserted pulse width td td t sclk t f atapi_dior data hold n/a 0 t g(write) atapi_diow data setup td td t sclk C (t sk1 + t sk2 + t sk4 ) t g(read) atapi_dior data setup td t od + t sud + 2 t bd + t cdd + t cdc t h atapi_diow data hold tk tk t sclk C (t sk1 + t sk2 + t sk4 ) t i atapi_dmack to atapi_dior /atapi_diow setup tm tm t sclk C (t sk1 + t sk2 + t sk4 ) t j atapi_dior /atapi_diow to atapi_dmack hold tk, teoc_mdma (tk + teoc_mdma) t sclk C (t sk1 + t sk2 + t sk4 ) t kr atapi_dior negated pulse width tkr tkr t sclk t kw atapi_diow negated pulse width tkw tkw t sclk t lr atapi_dior to atapi_dmarq delay n/a (td + tk) t sclk C (t od + 2 t bd + 2 t cdc ) t m atapi_cs0-1 valid to atapi_dior /atapi_diow tm tm t sclk C (t sk1 + t sk2 + t sk4 ) t n atapi_cs0-1 hold tk, teoc_mdma (tk + teoc_mdma) t sclk C (t sk1 + t sk2 + t sk4 ) 1 atapi timing register setting should be programmed with a value that guarantees parameter compliance with the ata ansi specific ation for an ata device mode of operation.
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 77 of 100 | may 2011 note that in figure 49 an alternate atapi_d0C15 port bus is atapi_d0C15a. figure 49. initiating a multiword dma data burst figure 50. sustained multiword dma data burst t m t i t d t g t f t g t h atapi_dmarq atapi_cs0 atapi_cs1 atapi_dmack atapi_dior atapi_diow atapi_d0C15 (read) atapi_d0C15 (write) atapi_dmarq atapi_d0C15 atapi_d0C15 atapi_cs0 atapi_cs1 atapi_dior atapi_diow t 0 t d t g t f t g t h t g t h t g t f t k (read) (write) atapi_dmack
rev. d | page 78 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 figure 51. device terminating a multiword dma data burst figure 52. host terminating a multiword dma data burst atapi_dmarq atapi_d0C15 atapi_d0C15 atapi_cs0 atapi_cs1 atapi_dmack atapi_dior atapi_diow t n t 0 t d t j t g t f t lr t g t h t kr t kw (read) (write) atapi_dmarq atapi_d0C15 atapi_d0C15 atapi_cs0 atapi_cs1 atapi_dmack atapi_dior atapi_diow t 0 t n t kr t kw t d t j t g t f t g t h (read) (write)
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 79 of 100 | may 2011 atapi ultra dma data-in transfer timing table 60 and figure 53 through figure 56 describe the atapi ultra dma data-in data transfer timing. the material in these figures is adapted from atapi-6 (incits 361-2002[r2007] and is used with permission of the american national stan- dards institute (ansi) on behalf of the information technology industry council (itic). co pies of atapi-6 (incits 361- 2002[r2007] can be purchased from ansi. table 60. atapi ultra dma data-in transfer timing atapi parameter atapi_ultra_tim_x timing register setting 1 timing equation t ds data setup time at host n/a t sk3 + t sudu t dh data hold time at host n/a t sk3 + t hdu t cvs crc word valid setup time at host tdvs tdvs t sclk C (t sk1 + t sk2 ) t cvh crc word valid hold time at host tack tack t sclk C (t sk1 + t sk2 ) t li limited interlock time n/a 2 t bd + 2 t sclk + t od t mli interlock time with minimum tzah, tcvs (tzah + tcvs) t sclk C (4 t bd + 4 t sclk + 2 t od ) t az maximum time allowed for output drivers to release n/a 0 t zah minimum delay time required for output tzah 2 t sclk + tzah t sclk + t sclk t env 2 atapi_dmack to atapi_dior /diow tenv (tenv t sclk ) +/C (t sk1 + t sk2 ) t rp atapi_dmack to atapi_dior /diow trp trp t sclk C (t sk1 + t sk2 + t sk4 ) t ack setup and hold times for atapi_dmack tack tack t sclk C (t sk1 + t sk2 ) 1 atapi timing register setting should be programmed with a value that guarantees parameter compliance with the ata ansi specific ation for ata device mode of operation. 2 this timing equation can be used to calculate both the minimum and maximum t env .
rev. d | page 80 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 in figure 53 and figure 54 an alternate atapi_d0C15 port bus is atapi_d0C15a. also note that atapi_addr pins include a1-3, atapi_cs0 , and atapi_cs1 . alternate atapi port atapi _addr pins include atapi_a0a, atapi_a1a, atapi_a2a, atapi_cs0 , and atapi_cs1 . figure 53. initiating an ultra dma data-in burst figure 54. sustained ultra dma data-in burst atapi_dmarq atapi_iordy atapi_d0C15 atapi addr t env t ack t env t ack t az t ack atapi_dmack atapi_diow atapi_dior atapi_iordy atapi_d0C15 t dh t dh t ds t dh t ds
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 81 of 100 | may 2011 figure 55. device terminating an ultra dma data-in burst figure 56. host terminating an ultra dma data-in burst atapi_dmarq atapi_iordy atapi_d0C15 atapi addr atapi_dmack atapi_diow atapi_dior t mli t ack t ack t li t li t li t zah t az t cvs t cvh t ack atapi_dmarq atapi_iordy atapi_d0C15 atapi addr atapi_dmack atapi_diow atapi_dior t li t mli t zah t rp t ack t ack t ack t li t cvs t cvh
rev. d | page 82 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 atapi ultra dma data-out transfer timing table 61 and figure 57 through figure 60 describes the atapi ultra dma data-out transfer timing. the material in these fig- ures is adapted from atapi- 6 (incits 361-2002[r2007] and is used with permission of the am erican national standards insti- tute (ansi) on behalf of the information technology industry council (itic). copies of atapi-6 (incits 361-2002 [r2007] can be purchased from ansi. table 61. atapi ultra dma data-out transfer timing atapi parameter atapi_ultra_tim_x timing register setting 1 timing equation t cyc 2 cycle time tdvs, tcyc_tdvs (tdvs + tcyc_tdvs) t sclk t 2cyc two cycle time tdvs, tcyc_tdvs 2 (tdvs + tcyc_tdvs) t sclk t dvs data valid setup time at sender tdvs tdvs t sclk C (t sk1 + t sk2 ) t dvh data valid hold time at sender tcyc_tdvs tcyc_tdvs t sclk C (t sk1 + t sk2 ) t cvs crc word valid setup time at host tdvs tdvs t sclk C (t sk1 + t sk2 ) t cvh crc word valid hold time at host tack tack t sclk C (t sk1 + t sk2 ) t dzfs time from data output re leased-to-driving to first strobe timing tdvs tdvs t sclk C (t sk1 + t sk2 ) t li limited interlock time n/a 2 t bd + 2 t sclk + t od t mli interlock time with minimum tmli tmli t sclk C (t sk1 + t sk2 ) t env 3 atapi_dmack to atapi_dior /diow tenv (tenv t sclk ) +/C (t sk1 + t sk2 ) t rfs ready to final strobe time n/a 2 t bd + 2 t sclk + t od t ack setup and hold time for atapi_dmack tack tack t sclk C (t sk1 + t sk2 ) t ss time from strobe edge to assertion of atapi_diow tss tss t sclk C (t sk1 + t sk2 ) 1 atapi timing register setting should be programmed with a value that guarantees parameter compliance with the ata ansi specific ation for ata device mode of operation. 2 ata/atapi-6 compliant functionality with limited speed. 3 this timing equation can be used to calculate both the minimum and maximum t env .
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 83 of 100 | may 2011 in figure 57 and figure 58 an alternate atapi_d0C15 port bus is atapi_d0C15a. figure 57. initiating an ultra dma data-out burst figure 58. sustained ultra dma data-out burst atapi_dmarq atapi_iordy atapi addr atapi_d0C15 t env t ack t ack atapi_dmack atapi_diow atapi_dior t li t dvs t dvh t dzfs atapi_d0C15 atapi_dior t 2cyc t cyc t dvh t dvh t dvh t dvs t dvs t cyc t 2cyc
rev. d | page 84 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 figure 59. host terminating an ultra dma data-out burst figure 60. device terminating an ultra dma data-out burst atapi_dmarq atapi_iordy atapi addr atapi_d0C15 atapi_dmack atapi_diow atapi_dior t li t li t ss t mli t li t ack t ack t ack t cvs t cvh atapi_dmarq atapi_iordy atapi addr atapi_d0C15 atapi_dmack atapi_diow atapi_dior t li t ack t mli t rfs t cvs t cvh t ack t li t ack t mli
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 85 of 100 | may 2011 usb on-the-go-dual-role device controller timing table 62 describes the usb on-the -go dual-role device con- troller timing requirements. jtag test and emulation port timing table 63 and figure 61 describe jtag port operations. table 62. usb on-the-go dual-role device controller timing requirements parameter min max unit timing requirements f usb usb_xi frequency 9 33.3 mhz fs usb usb_xi clock frequency stability C50 +50 ppm table 63. jtag port timing parameter min max unit timing parameters t tck tck period 20 ns t stap tdi, tms setup before tck high 4 ns t htap tdi, tms hold after tck high 4 ns t ssys system inputs setup before tck high 1 4ns t hsys system inputs hold after tck high 1 11 ns t trstw trst pulse-width 2 (measured in tck cycles) 4 t tck switching characteristics t dtdo tdo delay from tck low 10 ns t dsys system outputs delay after tck low 3 016.5ns 1 system inputs = pa15?0, pb14?0, pc13?0, pd15?0, pe15?0, pf15?0, pg15?0, ph13?0, pi15?0, pj13?0, dq15?0, dqs1?0, d15?0, atapi_pd iag , reset , nmi , and bmode3?0. 2 50 mhz maximum 3 system outputs = pa15?0, pb14?0, pc13?0, pd15?0, pe15?0, pf15?0, pg15?0, ph13?0, pi15?0, pj13?0, dq15?0, dqs1?0, d15?0, da12?0, dba1?0, dqm1?0, dclk0-1, dclk0?1 , dcs1?0 , dclke, dras , dcas , dwe , ams3?0 , abe1?0 , aoe , are , awe , clkout, a3?1, and mfs. figure 61. jtag port timing tck tms tdi tdo system inputs system outputs t tck t stap t htap t dtdo t ssys t hsys t dsys
rev. d | page 86 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 output drive currents figure 62 through figure 71 show typical current-voltage char- acteristics for the output driver s of the adsp-bf54x blackfin processors. the curves represent the current drive capability of the output drivers as a fu nction of output voltage. figure 62. drive current a (low v ddext ) figure 63. drive current a (high v ddext ) figure 64. drive current b (low v ddext ) C100 C80 C60 C40 C20 0 20 40 60 80 100 0 0.5 1.0 1.5 2.0 2.5 3.0 source voltage (v) source current (ma) vol voh 2.25v, +105c 2.5v, +25c 2.75v, C40c 2.25v, +105c 2.5v, +25c 2.75v, C40c C150 C100 C50 0 50 100 150 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 source voltage (v) source current (ma) voh vol 2.7v, +105c 3.3v, +25c 3.6v, C40c 2.7v, +105c 3.3v, +25c 3.6v, C40c C150 C100 C50 0 50 100 150 0 0.5 1.0 1.5 2.0 2.5 3.0 source voltage (v) source current (ma) voh vol 2.25v, +105c 2.5v, +25c 2.75v, C40c 2.25v, +105c 2.5v, +25c 2.75v, C40c figure 65. drive current b (high v ddext ) figure 66. drive current c (low v ddext ) figure 67. drive current c (high v ddext ) C250 C200 C150 C100 C50 0 50 100 150 200 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 source voltage (v) source current (ma) voh vol 2.7v, +105c 3.3v, +25c 3.6v, C40c 2.7v, +105c 3.3v, +25c 3.6v, C40c C80 C60 C40 C20 0 20 40 60 0 0.5 1.0 1.5 2.0 2.5 3.0 source voltage (v) source current (ma) voh vol 2.25v, +105c 2.5v, +25c 2.75v, C40c 2.25v, +105c 2.5v, +25c 2.75v, C40c C100 C80 C60 C40 C20 0 20 40 60 80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 output voltage (v) output current (ma) voh vol 2.7v, +105c 3.3v, +25c 3.6v, C40c 2.7v, +105c 3.3v, +25c 3.6v, C40c
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 87 of 100 | may 2011 figure 68. drive current d (ddr sdram) figure 69. drive current d (mobile ddr sdram) figure 70. drive current e (low v ddext ) C50 C40 C30 C20 C10 0 10 20 30 40 50 0 0.5 1.0 1.5 2.0 2.5 3. 0 source voltage (v) source current (ma) voh vol 2.6v, +25c 2.7v, C40c 2.6v, +25c 2.7v, C40c 2.5v, +105c 2.5v, C105c C50 C40 C30 C20 C10 0 10 20 30 40 50 0 0.25 0.5 0.75 1.0 1.25 2.0 source voltage (v) source current (ma) voh vol 1.875v, +25c 1.95v, C40c 1.875v, +25c 1.95v, C40c 1.8v, +105c 1.8v, +105c 1.5 1.75 C60 C50 C40 C30 C20 C10 0 10 0 0.5 1.0 1.5 2.0 2.5 3.0 source voltage (v) source current (ma) vol 2.25v, +105c 2.5v, +25c 2.75v, C40c figure 71. drive current e (high v ddext ) C90 C80 C70 C60 C50 C40 C30 C20 C10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 source voltage (v) source current (ma) vol 2.7v, +105c 3.3v, +25c 3.6v, C40c
rev. d | page 88 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 test conditions all timing parameters appearing in this data sheet were mea- sured under the conditions described in this section. figure 72 shows the measurement point fo r ac measurements (except output enable/disable). the measurement point v meas is v ddext /2 or v ddddr /2, depending on the pin under test. output enable time output pins are considered to be enabled when they have made a transition from a high-impedance state to the point when they start driving. the output enable time t ena is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown in the output enable/disable diagram ( figure 73 ). the time, t ena_measured , is the interval from th e point when the reference signal switches to the point wh en the output voltage reaches either 1.75 v (output high) or 1.25 v (output low). time t trip is the interval from when the outp ut starts driving to when the output reaches the 1.25 v or 1.75 v trip voltage. time t ena is calculated as shown in the equation: if multiple pins (such as the da ta bus) are enab led, the measure- ment value is that of the first pin to start driving. output disable time output pins are considered to be disabled when they stop driv- ing, go into a high-impedance state, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by v is dependent on the capacitive load, c l and the load current, i l . this decay time can be approximated by the equation: the output disable time t dis is the difference between t dis_measured and t decay as shown in figure 73 . the time t dis_measured is the interval from when the reference signal switches to when the output voltage decays v from the mea- sured output high or output low voltage. the time t decay is calculated with test loads c l and i l , and with v equal to 0.25 v. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose v to be the difference between the adsp-bf54x blackfin proces- sors output voltage and the input threshold for the device requiring the hold time. a typical v will be 0.4 v. c l is the total bus capacitance (per data line), and i l is the total leakage or three-state current (per data li ne). the hold time will be t decay plus the minimum disable time (for example, t ddat for an asyn- chronous memory write cycle). capacitive loading output delays and holds are based on standard capacitive loads of an average of 6 pf on all balls (see figure 74 ). v load is equal to v ddext /2 or v ddddr /2, depending on the pin under test. figure 72. voltage reference levels for ac measurements (except output enable/disable) input or output v meas v meas t ena t ena_measured t trip ? = t decay c l v () i l ? = figure 73. output enable/disable figure 74. equivalent device loading for ac measurements (includes all fixtures) reference signal t dis output starts driving v oh (measured) v v ol (measured) + v t dis_measured v oh (measured) v ol (measured) v trip (high) v oh (measured ) v ol (measured) high impedance state output stops driving t ena t decay t ena_measured t trip v trip (low) t1 zo = 50 (impedance) td = 4.04 1.18 ns 2pf tester pin electronics 50 0.5pf 70 400 45 4pf notes: the worst-case transmission line delay is shown and can be used for the output timing analysis to refelect the transmission line effect and must be considered. the transmission line (td), is for load only and does not affect the data sheet timing specifications. analog devices recommends using the ibis model timing for a given system requirement. if necessary, a system may incorporate external drivers to compensate for any timing differences. v load dut output 50
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 89 of 100 | may 2011 typical rise and fall times figure 75 through figure 86 on page 91 show how output rise time varies with capacitance. th e delay and hold specifications given should be derated by a factor derived from these figures. the graphs in these figures may not be linear outside the ranges shown. figure 75. typical rise and fall times (10% to 90%) vs. load capacitance for driver a at v ddext = 2.25 v figure 76. typical rise and fall times (10% to 90%) vs. load capacitance for driver a at v ddext = 3.65 v load capacitance (pf) rise time rise and fall time ns (10% to 90%) 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10% to 90%) 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time figure 77. typical rise and fall times (10% to 90%) vs. load capacitance for driver b at v ddext = 2.25 v figure 78. typical rise and fall times (10% to 90%) vs. load capacitance for driver b at v ddext = 3.65 v load capacitance (pf) rise time rise and fall time ns (10% to 90%) 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10% to 90%) 10 9 8 7 6 5 4 3 2 1 0 0 50 100 150 200 250 fall time
rev. d | page 90 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 figure 79. typical rise and fall times (10% to 90%) vs. load capacitance for driver c at v ddext = 2.25 v figure 80. typical rise and fall times (10% to 90%) vs. load capacitance for driver c at v ddext = 3.65 v figure 81. typical rise and fall times (10% to 90%) vs. load capacitance for driver d ddr sdram at v ddddr = 2.5v load capacitance (pf) rise time rise and fall time ns (10% to 90%) 25 30 20 15 10 5 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10% to 90%) 20 18 16 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time load capacitance (pf) rise/fall time rise and fall time ns (10% to 90%) 5 6 4 3 2 1 0 010203040506070 figure 82. typical rise and fall times (10% to 90%) vs. load capacitance for driver d ddr sdram at v ddddr = 2.7v figure 83. typical rise and fall times (10% to 90%) vs. load capacitance for driver d mobile ddr sdram at v ddddr = 1.8v figure 84. typical rise and fall times (10% to 90%) vs. load capacitance for driver d mobile ddr sdram at v ddddr = 1.95v load capacitance (pf) rise/fall time rise and fall time ns (10% to 90%) 5 6 4 3 2 1 0 010203040 70 50 60 load capacitance (pf) rise/fall time rise and fall time ns (10% to 90%) 2.5 3 2 1.5 1 .5 0 010203040506070 3.5 4 load capacitance (pf) rise/fall time rise and fall time ns (10% to 90%) 2.5 3 2 1.5 1 .5 0 010203040506070 3.5 4
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 91 of 100 | may 2011 thermal characteristics to determine the junction te mperature on the application printed circuit board use where: t j =junction temperature (c) t case = case temperature (c) meas ured by customer at top cen- ter of package. jt = from table 72 p d = power dissipation. (see table 17 on page 37 for a method to calculate p d .) values of ja are provided for packag e comparison and printed circuit board design considerations. ja can be used for a first order approximation of t j by the equation where: t a = ambient temperature (c) table 64 lists values for jc and jb parameters. th ese values are provided for package comparis on and printed circuit board design considerations. ai rflow measurements in table 64 com- ply with jedec standards je sd51-2 and jesd51-6, and the junction-to-board measurement complies with jesd51-8. the junction-to-case me asurement complies with mil-std-883 (method 1012.1). all measur ements use a 2s2p jedec testboard. figure 85. typical fall time (10% to 90%) vs . load capacitance for driver e at v ddext = 2.7 v figure 86. typical fall time (10% to 90%) vs . load capacitance for driver e at v ddext = 3.65 v load capacitance (pf) fall time ns (10% to 90%) 132 128 124 120 116 108 0 50 100 150 200 250 fall time 112 load capacitance (pf) fall time ns (10% to 90%) 124 120 116 112 108 100 0 50 100 150 200 250 fall time 104 table 64. thermal characteristics, 400-ball csp_bga parameter condition typical unit ja 0 linear m/s air flow 18.4 c/w 1 linear m/s air flow 15.8 c/w 2 linear m/s air flow 15.0 c/w jb 9.75 c/w jc 6.37 c/w jt 0 linear m/s air flow 0.27 c/w 1 linear m/s air flow 0.60 c/w 2 linear m/s air flow 0.66 c/w t j t case jt p d () + = t j t a ja p d () + =
rev. d | page 92 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 400-ball csp_bga package table 65 lists the csp_bga pac kage by signal for the adsp-bf549. table 66 on page 95 lists the csp_bga package by ball number. table 65. 400-ball csp_bga ball assignment (alphabetical by signal) signal ball no. signal ball no. signal ball no. signal ball no. a1 b2 da4 g16 dqs1 h18 gnd l10 a2 a2 da5 f19 dras e17 gnd l11 a3 b3 da6 d20 dwe e18 gnd l12 abe0 c17 da7 c20 emu r5 gnd l13 abe1 c16 da8 f18 ext_wake m18 gnd l14 ams0 a10 da9 e19 gnd a1 gnd m6 ams1 d9 da10 b20 gnd a13 gnd m7 ams2 b10 da11 f17 gnd a20 gnd m8 ams3 d10 da12 d19 gnd b11 gnd m9 aoe c10 dba0 h17 gnd d1 gnd m10 are b12 dba1 h16 gnd d4 gnd m11 atapi_pdiag p19 dcas f16 gnd e3 gnd m12 awe d12 dclk0 e16 gnd f3 gnd m13 bmode0 w1 dclk0 d16 gnd f6 gnd m14 bmode1 w2 dclk1 c18 gnd f14 gnd n6 bmode2 w3 dclk1 d18 gnd g9 gnd n7 bmode3 w4 dclke b18 gnd g10 gnd n8 clkbuf d11 dcs0 c19 gnd g11 gnd n9 clkin a11 dcs1 b19 gnd h7 gnd n10 clkout l16 ddr_vref m20 gnd h8 gnd n11 d0 d13 ddr_vssr n20 gnd h9 gnd n12 d1 c13 dq0 l18 gnd h10 gnd n13 d2 b13 dq1 m19 gnd h11 gnd n14 d3 b15 dq2 l19 gnd h12 gnd p8 d4 a15 dq3 l20 gnd j7 gnd p9 d5 b16 dq4 l17 gnd j8 gnd p10 d6 a16 dq5 k16 gnd j9 gnd p11 d7 b17 dq6 k20 gnd j10 gnd p12 d8 c14 dq7 k17 gnd j11 gnd p13 d9 c15 dq8 k19 gnd j12 gnd r9 d10 a17 dq9 j20 gnd k7 gnd r13 d11 d14 dq10 k18 gnd k8 gnd r14 d12 d15 dq11 h20 gnd k9 gnd r16 d13 e15 dq12 j19 gnd k10 gnd u8 d14 e14 dq13 j18 gnd k11 gnd v6 d15 d17 dq14 j17 gnd k12 gnd y1 da0 g19 dq15 j16 gnd k13 gnd y20 da1 g17 dqm0 g20 gnd l7 gnd mp e7 da2 e20 dqm1 h19 gnd l8 mfs e6 da3 g18 dqs0 f20 gnd l9 mlf_m f4
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 93 of 100 | may 2011 mlf_p e4 pc5 g1 pe15 w17 ph7 h4 mxi c2 pc6 j5 pf0 k3 ph8 d5 mxo c1 pc7 h3 pf1 j1 ph9 c4 nmi c11 pc8 y14 pf2 k2 ph10 c7 pa0 u12 pc9 v13 pf3 k1 ph11 c5 pa1 v12 pc10 u13 pf4 l2 ph12 d7 pa2 w12 pc11 w14 pf5 l1 ph13 c6 pa3 y12 pc12 y15 pf6 l4 pi0 a3 pa4 w11 pc13 w15 pf7 k4 pi1 b4 pa5 v11 pd0 p3 pf8 l3 pi2 a4 pa6 y11 pd1 p4 pf9 m1 pi3 b5 pa7 u11 pd2 r1 pf10 m2 pi4 a5 pa8 u10 pd3 r2 pf11 m3 pi5 b6 pa9 y10 pd4 t1 pf12 m4 pi6 a6 pa10 y9 pd5 r3 pf13 n4 pi7 b7 pa11 v10 pd6 t2 pf14 n1 pi8 a7 pa12 y8 pd7 r4 pf15 n2 pi9 c8 pa13 w10 pd8 u1 pg0 j4 pi10 b8 pa14 y7 pd9 u2 pg1 k5 pi11 a8 pa15 w9 pd10 t3 pg2 l5 pi12 a9 pb0 w5 pd11 v1 pg3 n3 pi13 c9 pb1 y2 pd12 t4 pg4 p1 pi14 d8 pb2 t6 pd13 v2 pg5 v15 pi15 b9 pb3u6pd14u4pg6y17pj0r20 pb4 y4 pd15 u3 pg7 w16 pj1 n18 pb5 y3 pe0 v19 pg8 v16 pj2 m16 pb6 w6 pe1 t17 pg9 y19 pj3 t20 pb7 v7 pe2 u18 pg10 y18 pj4 n17 pb8 w8 pe3 v14 pg11 u15 pj5 u20 pb9 v8 pe4 y16 pg12 p16 pj6 p18 pb10 u7 pe5 w20 pg13 r18 pj7 n16 pb11 w7 pe6 w19 pg14 y13 pj8 r19 pb12 y6 pe7 r17 pg15 w13 pj9 p17 pb13 v9 pe8 v20 ph0 w18 pj10 t19 pb14 y5 pe9 u19 ph1 u14 pj11 m17 pc0 h2 pe10 t18 ph2 v17 pj12 p20 pc1 j3 pe11 p2 ph3 v18 pj13 n19 pc2 j2 pe12 m5 ph4 u17 reset c12 pc3 h1 pe13 p5 ph5 c3 rtxi a14 pc4 g2 pe14 u16 ph6 d6 rtxo b14 table 65. 400-ball csp_bga ball assignment (alphabetical by signal) (continued) signal ball no. signal ball no. signal ball no. signal ball no.
rev. d | page 94 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 tck v3 v ddddr j14 v ddext n5 v ddint g13 tdi v5 v ddddr j15 v ddext n15 v ddint j6 tdo v4 v ddddr k14 v ddext p15 v ddint j13 tms u5 v ddddr k15 v ddext r6 v ddint l6 trst t5 v ddext e5 v ddext r7 v ddint l15 usb_dm e2 v ddext e9 v ddext r8 v ddint p6 usb_dp e1 v ddext e10 v ddext r15 v ddint p7 usb_id g3 v ddext e11 v ddext t7 v ddint p14 usb_rset d3 v ddext e12 v ddext t8 v ddint r10 usb_vbus d2 v ddext f7 v ddext t9 v ddint r11 usb_vref b1 v ddext f8 v ddext t10 v ddint r12 usb_xi f1 v ddext f13 v ddext t11 v ddint u9 usb_xo f2 v ddext g5 v ddext t12 v ddmp e8 v ddddr f10 v ddext g6 v ddext t13 v ddrtc e13 v ddddr f11 v ddext g7 v ddext t14 v ddusb f5 v ddddr f12 v ddext g14 v ddext t15 v ddusb g4 v ddddr g15 v ddext h5 v ddext t16 v ddvr f15 v ddddr h13 v ddext h6 v ddint f9 vr out0 a18 v ddddr h14 v ddext k6 v ddint g8 vr out1 a19 v ddddr h15 v ddext m15 v ddint g12 xtal a12 table 65. 400-ball csp_bga ball assignment (alphabetical by signal) (continued) signal ball no. signal ball no. signal ball no. signal ball no.
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 95 of 100 | may 2011 table 66 lists the csp_bga packag e by ball number for the adsp-bf549. table 65 on page 92 lists the csp_bga package by signal. table 66. 400-ball csp_bga ball assignment (numerical by ball number) ball no. signal ball no. signal ball no. signal ball no. signal a1 gnd c1 mxo e1 usb_dp g1 pc5 a2 a2 c2 mxi e2 usb_dm g2 pc4 a3 pi0 c3 ph5 e3 gnd g3 usb_id a4 pi2 c4 ph9 e4 mlf_p g4 v ddusb a5 pi4 c5 ph11 e5 v ddext g5 v ddext a6 pi6 c6 ph13 e6 mfs g6 v ddext a7 pi8 c7 ph10 e7 gnd mp g7 v ddext a8 pi11 c8 pi9 e8 v ddmp g8 v ddint a9 pi12 c9 pi13 e9 v ddext g9 gnd a10 ams0 c10 aoe e10 v ddext g10 gnd a11 clkin c11 nmi e11 v ddext g11 gnd a12 xtal c12 reset e12 v ddext g12 v ddint a13 gnd c13 d1 e13 v ddrtc g13 v ddint a14 rtxi c14 d8 e14 d14 g14 v ddext a15 d4 c15 d9 e15 d13 g15 v ddddr a16 d6 c16 abe1 e16 dclk0 g16 da4 a17 d10 c17 abe0 e17 dras g17 da1 a18 vrout 0 c18 dclk1 e18 dwe g18 da3 a19 vrout 1 c19 dcs0 e19 da9 g19 da0 a20 gnd c20 da7 e20 da2 g20 dqm0 b1 usb_vref d1 gnd f1 usb_xi h1 pc3 b2 a1 d2 usb_vbus f2 usb_xo h2 pc0 b3 a3 d3 usb_rset f3 gnd h3 pc7 b4 pi1 d4 gnd f4 mlf_m h4 ph7 b5 pi3 d5 ph8 f5 v ddusb h5 v ddext b6 pi5 d6 ph6 f6 gnd h6 v ddext b7 pi7 d7 ph12 f7 v ddext h7 gnd b8 pi10 d8 pi14 f8 v ddext h8 gnd b9 pi15 d9 ams1 f9 v ddint h9 gnd b10 ams2 d10 ams3 f10 v ddddr h10 gnd b11 gnd d11 clkbuf f11 v ddddr h11 gnd b12 are d12 awe f12 v ddddr h12 gnd b13 d2 d13 d0 f13 v ddext h13 v ddddr b14 rtxo d14 d11 f14 gnd h14 v ddddr b15 d3 d15 d12 f15 v ddvr h15 v ddddr b16 d5 d16 dclk0 f16 dcas h16 dba1 b17 d7 d17 d15 f17 da11 h17 dba0 b18 dclke d18 dclk1 f18 da8 h18 dqs1 b19 dcs1 d19 da12 f19 da5 h19 dqm1 b20 da10 d20 da6 f20 dqs0 h20 dq11
rev. d | page 96 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 j1 pf1 l1 pf5 n1 pf14 r1 pd2 j2 pc2 l2 pf4 n2 pf15 r2 pd3 j3 pc1 l3 pf8 n3 pg3 r3 pd5 j4 pg0 l4 pf6 n4 pf13 r4 pd7 j5 pc6 l5 pg2 n5 v ddext r5 emu j6 v ddint l6 v ddint n6 gnd r6 v ddext j7 gnd l7 gnd n7 gnd r7 v ddext j8 gnd l8 gnd n8 gnd r8 v ddext j9 gnd l9 gnd n9 gnd r9 gnd j10 gnd l10 gnd n10 gnd r10 v ddint j11 gnd l11 gnd n11 gnd r11 v ddint j12 gnd l12 gnd n12 gnd r12 v ddint j13 v ddint l13 gnd n13 gnd r13 gnd j14 v ddddr l14 gnd n14 gnd r14 gnd j15 v ddddr l15 v ddint n15 v ddext r15 v ddext j16 dq15 l16 clkout n16 pj7 r16 gnd j17 dq14 l17 dq4 n17 pj4 r17 pe7 j18 dq13 l18 dq0 n18 pj1 r18 pg13 j19 dq12 l19 dq2 n19 pj13 r19 pj8 j20 dq9 l20 dq3 n20 ddr_vssr r20 pj0 k1 pf3 m1 pf9 p1 pg4 t1 pd4 k2 pf2 m2 pf10 p2 pe11 t2 pd6 k3 pf0 m3 pf11 p3 pd0 t3 pd10 k4 pf7 m4 pf12 p4 pd1 t4 pd12 k5 pg1 m5 pe12 p5 pe13 t5 trst k6 v ddext m6 gnd p6 v ddint t6 pb2 k7 gnd m7 gnd p7 v ddint t7 v ddext k8 gnd m8 gnd p8 gnd t8 v ddext k9 gnd m9 gnd p9 gnd t9 v ddext k10 gnd m10 gnd p10 gnd t10 v ddext k11 gnd m11 gnd p11 gnd t11 v ddext k12 gnd m12 gnd p12 gnd t12 v ddext k13 gnd m13 gnd p13 gnd t13 v ddext k14 v ddddr m14 gnd p14 v ddint t14 v ddext k15 v ddddr m15 v ddext p15 v ddext t15 v ddext k16 dq5 m16 pj2 p16 pg12 t16 v ddext k17 dq7 m17 pj11 p17 pj9 t17 pe1 k18 dq10 m18 ext_wake p18 pj6 t18 pe10 k19 dq8 m19 dq1 p19 atapi_pdiag t19 pj10 k20 dq6 m20 ddr_vref p20 pj12 t20 pj3 table 66. 400-ball csp_bga ball assignment (numerical by ball number) (continued) ball no. signal ball no. signal ball no. signal ball no. signal
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 97 of 100 | may 2011 figure 87 shows the top view of the bga ball configuration. u1 pd8 v1 pd11 w1 bmode0 y1 gnd u2 pd9 v2 pd13 w2 bmode1 y2 pb1 u3 pd15 v3 tck w3 bmode2 y3 pb5 u4 pd14 v4 tdo w4 bmode3 y4 pb4 u5 tms v5 tdi w5 pb0 y5 pb14 u6 pb3 v6 gnd w6 pb6 y6 pb12 u7 pb10 v7 pb7 w7 pb11 y7 pa14 u8 gnd v8 pb9 w8 pb8 y8 pa12 u9 v ddint v9 pb13 w9 pa15 y9 pa10 u10 pa8 v10 pa11 w10 pa13 y10 pa9 u11 pa7 v11 pa5 w11 pa4 y11 pa6 u12 pa0 v12 pa1 w12 pa2 y12 pa3 u13 pc10 v13 pc9 w13 pg15 y13 pg14 u14 ph1 v14 pe3 w14 pc11 y14 pc8 u15 pg11 v15 pg5 w15 pc13 y15 pc12 u16 pe14 v16 pg8 w16 pg7 y16 pe4 u17 ph4 v17 ph2 w17 pe15 y17 pg6 u18 pe2 v18 ph3 w18 ph0 y18 pg10 u19 pe9 v19 pe0 w19 pe6 y19 pg9 u20 pj5 v20 pe8 w20 pe5 y20 gnd table 66. 400-ball csp_bga ball assignment (numerical by ball number) (continued) ball no. signal ball no. signal ball no. signal ball no. signal figure 87. 400-ball csp_bga configuration (top view) a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 1011121314 1617181920 15 v ddext gnd v ddint i/o signals key: references: ddr_v ref ,usb_v ref r t u v w y nc s g r grounds: gnd mp ,ddr_v ssr supplies: v ddddr ,v ddmp ,v ddusb ,v ddrtc vv s g r s g r ss ss s s ss s s s s s v ddvr , s vr out v
rev. d | page 98 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 outline dimensions dimensions for the 17 mm 17 mm csp_bga package in figure 88 are shown in millimeters. surface-mount design table 67 is provided as an aid to pcb design. for industry-stan- dard design recommendations, refer to ipc-7351, generic requirements for surface-mount design and land pattern standard . figure 88. 400-ball, 17 mm 17 mm csp_bga (chip scale package ball grid array) (bc-400-1) dimensions shown in millimeters. compliant to jedec standards mo-275-mmab-1. detail a top view detail a coplanarity 0.20 0.50 0.45 0.40 ball diameter seating plane a1 ball corner 0.80 bsc a b c d e f g h j k l m n p r 15 17 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bottom view 15.20 bsc sq 16 19 18 20 t u v w y 0.25 min 0.65 min 1.70 max 17.20 17.00 sq 16.80 table 67. bga data for use with surface-mount design package package ball attach type package solder mask opening package ball pad size 400-ball csp_bga (chip scale package ba ll grid array) bc-400-1 solder mask defined 0.40 mm diameter 0.50 mm diameter
adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 rev. d | page 99 of 100 | may 2011 automotive products the adsp-bf542, adsp-bf544, and the adsp-bf549 models are available with controlled manufacturing to support the qual- ity and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models and designers should review the product specifications section of this data sheet carefully. only the automotive grade products shown in table 68 are available for use in automotive applications. contact your local adi account representative for sp ecific product ordering infor- mation and to obtain the specific automotive reliability reports for these models. ordering guide table 68. automotive products product family 1, 2 temperature range 3 speed grade (max) package description package option ADBF542WBBCZ4XX C40c to +85c 400 mhz 400-ball csp_bga bc-400-1 adbf542wbbcz5xx C40c to +85c 533 mhz 400-ball csp_bga bc-400-1 adbf544wbbcz5xx C40c to +85c 533 mhz 400-ball csp_bga bc-400-1 adbf549wbbcz5xx C40c to +85c 533 mhz 400-ball csp_bga bc-400-1 adbf549mwbbcz5xx C40c to +85c 533 mhz 400-ball csp_bga bc-400-1 1 z = rohs compliant part. 2 the use of xx designates silicon revision. 3 referenced temperature is ambient temperature. model 1, 2, 3 1 each adsp-bf54xm model contains a mobile ddr controller and does not support the use of standard ddr memory. 2 z = rohs compliant part. 3 the adsp-bf549 is available for automotive use only. please contact your local adi product representative or authorized distrib utor for specific automotive product ordering information. temperature range 4, 5 4 referenced temperature is ambient temperature. 5 temperature range ?40c to +105c is classified as extended temperature range. speed grade (max) package description package option adsp-bf542bbcz-4a C40c to +85c 400 mhz 400-ball csp_bga bc-400-1 adsp-bf542bbcz-5a C40c to +85c 533 mhz 400-ball csp_bga bc-400-1 adsp-bf542mbbcz-5m C40c to +85c 533 mhz 400-ball csp_bga bc-400-1 adsp-bf542kbcz-6a 0c to +70c 600 mhz 400-ball csp_bga bc-400-1 adsp-bf544bbcz-4a C40c to +85c 400 mhz 400-ball csp_bga bc-400-1 adsp-bf544bbcz-5a C40c to +85c 533 mhz 400-ball csp_bga bc-400-1 adsp-bf544mbbcz-5m C40c to +85c 533 mhz 400-ball csp_bga bc-400-1 adsp-bf547bbcz-5a C40c to +85c 533 mhz 400-ball csp_bga bc-400-1 adsp-bf547mbbcz-5m C40c to +85c 533 mhz 400-ball csp_bga bc-400-1 adsp-bf547kbcz-6a 0c to +70c 600 mhz 400-ball csp_bga bc-400-1 adsp-bf547ybc-4a C40c to +105c 400 mhz 400-ball csp_bga bc-400-1 adsp-bf547ybcz-4a C40c to +105c 400 mhz 400-ball csp_bga bc-400-1 adsp-bf548mbbcz-5m C40c to +85c 533 mhz 400-ball csp_bga bc-400-1 adsp-bf548bbcz-5a C40c to +85c 533 mhz 400-ball csp_bga bc-400-1
rev. d | page 100 of 100 | may 2011 adsp-bf542/adsp-bf544/adsp-bf547/adsp-bf548/adsp-bf549 ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06512-0-5/11(d)

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